Device having interdigital capacitor

• US 20030183864A1
• Filed: 03/26/2003
• Published: 10/02/2003
• Est. Priority Date: 03/28/2002
• Status: Active Grant

• Current Assignee: Fujitsu Quantum Devices Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Quantum Devices Limited (Fujitsu Limited)
• Inventors: Miyazawa, Naoyuki
• Granted Patent: US 6,949,811 B2
• Time in Patent Office: Days
• US Class Current: 257/307
• CPC Class Codes: H01L 27/0805 Capacitors only

Abstract

A device includes a transistor, and two interdigital capacitors. The transistor is located on an imaginary extension line aligned with a common electrode of the two interdigital capacitors.

Claims

1. A device comprising:

a transistor; and

two interdigital capacitors,

the transistor being located on an imaginary extension line aligned with a common electrode of the two interdigital capacitors.

2. The device according to claim 1, wherein the common electrode has a straight line, which is connected to one of electrode regions of the transistor.

3. The device according to claim 1, wherein the common electrode is connected to one of electrode regions of the transistor via a straight interconnection line that continues to the common electrode.

4. The device according to claim 1, wherein the two interdigital capacitors comprise:

the common electrode having a bus line and electrode fingers running from the bus line in first and second directions;

a first comb-like electrode having electrode fingers that are alternately arranged with the electrode fingers of the common electrode running in the first direction; and

a second comb-like electrode having electrode fingers that are alternately arranged with the electrode fingers of the common electrode running in the second direction,

electrode regions of the transistor being located on the imaginary extension line aligned with the bus line of the common electrode.

5. The device according to claim 1, wherein the two interdigital capacitors comprise:

the common electrode having a bus line and electrode fingers running from the bus line in first and second directions;

a first comb-like electrode having electrode fingers that are alternately arranged with the electrode fingers of the common electrode running in the first direction; and

a second comb-like electrode having electrode fingers that are alternately arranged with the electrode fingers of the common electrode running in the second direction,

the bus line of the common electrode being connected to an electrode region of the transistor via a straight interconnection line that continues to the bus line.

6. The device according to claim 1, wherein the two interdigital capacitors comprise:

the common electrode having a bus line and electrode fingers running from the bus line in first and second directions;

a first comb-like electrode having electrode fingers that are alternately arranged with the electrode fingers of the common electrode running in the first direction; and

a second comb-like electrode having electrode fingers that are alternately arranged with the electrode fingers of the common electrode running in the second direction,

the bus line of the common electrode being connected to a first electrode region of the transistor, the first comb-like electrode being connected to a second electrode region of the transistor, and

the second comb-like electrode being connected to a control terminal of the transistor.

7. The device according to claim 1, wherein:

the common electrode has a bus line and electrode fingers that run in two directions; and

two electrode regions of the transistor being located on an imaginary extension line aligned with the bus line.

8. The device according to claim 1, wherein the transistor is close to electrode fingers that run from both sides of a bus line of the common electrode and are arranged in a line.

9. The device according to claim 1, wherein the two interdigital capacitors comprise:

the common electrode having a bus line connected to a first electrode region of the transistor, and first and second electrode fingers that run from the bus line in first and second directions;

a first comb-like electrode having electrode fingers that are alternately arranged with the electrode fingers of the common electrode running in the first direction;

a second com-like electrode having electrode fingers that are alternately arranged with the electrode fingers of the common electrode running in the second direction;

a first interconnection line connecting the first comb-like electrode to a second electrode region of the transistor; and

a second interconnection line connecting the second comb-like electrode to a control terminal of the transistor.

10. The device according to claims 9, wherein the electrode fingers that run from the bus line include electrode fingers that are close to and in parallel with the first and second interconnection lines so that the first and second interconnection lines can make a capacitance.

11. The device according to claim 10, wherein at least one of the first and second interconnection lines has a crank portion that is located close to the transistor and enables the first and second interconnection lines to be spaced apart from the electrode fingers close to the first and second interconnection lines by an identical distance.

12. The device according to claim 1, wherein the two interdigital capacitors comprise:

the common electrode having a bus line, m (m is a natural number) electrode fingers running from the bus line in a first direction, and n (n is a natural number and is not equal to m) electrode fingers running from the bus line in a second direction;

a first comb-like electrode having electrode fingers alternately arranged with the m electrode fingers; and

a second comb-like electrode having electrode fingers alternately arranged with the n electrode fingers,

the bus line being connected to one of two electrode regions of the transistor.

13. The device according to claim 1, wherein the two interdigital capacitors comprise:

the common electrode having a bus line connected to a first electrode region of the transistor, and first and second electrode fingers that run from the bus line in first and second directions;

a first comb-like electrode having electrode fingers alternately arranged with the m electrode fingers; and

a second comb-like electrode having electrode fingers alternately arranged with the n electrode fingers,

the bus line being connected to one of two electrode regions of the transistor,

the electrode fingers running in the first direction having a length different from that of the electrode fingers running in the second direction.

14. The device according to claim 1, wherein:

one of the two interdigital capacitors is connected between a gate and source of the transistor, and the other interdigital capacitor is connected between a drain and source of the transistor; and

the transistor and the two interdigital capacitors form an oscillator.

15. A device comprising:

first and second transistors;

first and second interdigital capacitors connected to the first transistor; and

third and fourth interdigital capacitors connected to the second transistor,

wherein;

the first transistor being located on an imaginary extension line continuing to a first common electrode of the first and second interdigital capacitors;

the second transistor being located on an imaginary extension line continuing to a second common electrode of the third and fourth interdigital capacitors; and

the second and third interdigital capacitors are formed by a third common electrode.

16. The device according to claim 15, wherein the first and second common electrodes have symmetry about the third common electrode.

17. The device according to claim 15, wherein the first and second common electrodes have symmetry about the third common electrode, and the first and second transistors have symmetry with respect to the third common electrode.

18. The device according to claim 15, wherein the first common electrode has a straight bus line connected to an electrode region of the first transistor;

and

the second common electrode has another straight bus line connected to an electrode region of the second transistor.

19. The device according to claim 15, wherein:

the first common electrode has a straight bus line connected to one of two electrode regions of the first transistor;

the second common electrode has another straight bus line connected to one to two electrode regions of the second transistor; and

the other electrode regions of the first and second transistors are connected via a straight interconnection line.

20. The device according to claim 15, wherein:

the first, second and third common electrodes respectively have bus lines;

electrode fingers run from each of the bus lines in first and second directions;

the electrode fingers that run from the bus line of the first common electrode in the second direction are alternately arranged with the electrode fingers that run from the bus line of the third common electrode in the first direction so that the second interdigital capacitor can be made;

the electrode fingers that run from the bus line of the third common electrode in the second direction are alternately arranged with the electrode fingers that run from the bus line of the second common electrode in the first direction so that the third interdigital capacitor can be made.

21. The device according to claim 15, wherein the first and second transistors and the first through fourth capacitors are elements of an oscillator.

22. The device according to claim 15, wherein the first and second transistors and the first through fourth capacitors are formed on a chip.

23. A device comprising:

first and second transistors;

first and second interdigital capacitors connected to the first transistor; and

third and fourth interdigital capacitors connected to the second transistor,

wherein;

the second and third interdigital capacitors have a first common electrode including a straight bus line; and

the first transistor and the first and second interdigital capacitors, and the second transistor and the third and fourth interdigital capacitors have symmetry about the first common electrode.

24. The device according to claim 23, wherein:

electrode regions of the first transistor are located on an imaginary extension line continuing to a second common electrode of the first and second interdigital capacitors; and

electrode regions of the second transistor are located on another imaginary extension line continuing to a third common electrode of the third and fourth interdigital capacitors.

25. The device according to claim 23, wherein the first and second transistors are connected via a straight interconnection line.

26. The device according to claim 23, wherein the first and second transistors and the first through fourth capacitors are elements of an oscillator.

27. The device according to claim 23, wherein the first and second transistors and the first through fourth capacitors are formed on a chip.

28. A device comprising:

first and second transistors;

first and second interdigital capacitors connected to the first transistor; and

third and fourth interdigital capacitors connected to the second transistor,

wherein;

the first and second interdigital capacitors have a first common electrode including a first straight bus line;

the third and fourth interdigital capacitors have a second common electrode including a second straight bus line; and

the first and second bus lines are arranged in a line.

29. The device according to claim 28, wherein the first and second transistors are close to each other and are located between the first and second common electrodes.

30. The device according to claim 28, wherein electrode regions of the first transistor and those of the second transistor are arranged on an imaginary line that connects the first and second common electrodes.

31. The device according to claim 28, wherein:

the first and second capacitors have electrode fingers that run from both sides of the first common electrode and are close to the first transistor; and

the third and fourth capacitors have electrode fingers that run from both sides of the second common electrode and are close to the second transistor.

32. The device according to claim 28, wherein the first and second transistors and the first through fourth capacitors are elements of an oscillator.

33. The device according to claim 28, wherein the first and second transistors and the first through fourth capacitors are formed on a chip.

34. A device comprising:

first and second transistors;

first and second interdigital capacitors connected to the first transistor; and

third and fourth interdigital capacitors connected to the second transistor,

wherein;

the first and second interdigital capacitors have a first common electrode including a first straight bus line;

the third and fourth interdigital capacitors have a second common electrode including a second straight bus line; and

a first circuit pattern including the first transistor and the first and second interdigital capacitors and a second circuit pattern including the second transistor and the third and fourth interdigital capacitors have axial symmetry.

35. The device according to claim 34, wherein the first and second transistors and the first through fourth capacitors are elements of an oscillator.

36. The device according to claim 34, wherein the first and second transistors and the first through fourth capacitors are formed on a chip.

37. A communication device comprising:

a circuit that processes a transmit or receive signal in synchronism with an oscillation signal; and

a device supplying the circuit with the oscillation signal,

the device comprising;

a transistor; and

two interdigital capacitors,

the transistor being located on an imaginary extension line aligned with a common electrode of the two interdigital capacitors.