Memory structures

• US 20030183868A1
• Filed: 04/02/2002
• Published: 10/02/2003
• Est. Priority Date: 04/02/2002
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Van Brocklin, Andrew L., Fricke, Peter, Koll, Andrew, Lazaroff, Dennis M.
• Application Number:
  US10/115,750
• Publication Number:
  US 20030183868A1
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Abstract

A memory structure that includes a first electrode, a second electrode having an edge, a third electrode, a control element disposed between the first electrode and the second electrode, and memory storage element disposed between the edge of the second electrode and the third electrode.

Claims

1. A memory structure comprising:

a first electrode;

a second electrode having an edge;

a third electrode;

a memory storage element disposed between said third electrode and said edge of said second electrode; and

a control element disposed between said second electrode and said first electrode.

2. The memory structure of claim 1 wherein said memory storage element comprises an antifuse device.

3. The memory structure of claim 1 wherein said memory storage element comprises a tunnel junction device.

4. The memory structure of claim 1 wherein said memory storage element comprises either a silicide switch or a LeCombre switch device.

5. The memory structure of claim 1 wherein said memory storage element is selected from the group consisting of an antifuse, a fuse, a charge storage device, a resistive material, a trap-induced hysteresis material, a ferroelectric capacitor material, a Hall effect material, and a tunneling magneto-resistive material.

6. The memory structure of claim 1 wherein said memory storage element comprises an antifuse including material from the group consisting of an oxidized metal tunnel junction, a silicon dioxide tunnel junction, a dielectric-rupture, a polysilicon semiconductor, a polycrystalline semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, a metal filament electro-migration semiconductor, and a polysilicon resistor semiconductor.

7. The memory structure of claim 1 wherein said memory storage element comprises a re-writable phase change material.

8. The memory structure of claim 1 wherein said control element comprises a tunnel junction device.

9. The memory structure of claim 1 wherein said control element comprises a diode.

10. The memory structure of claim 1 wherein said control element is selected from the group consisting of a recrystallized semiconductor, junction field effect transistor, a junction field effect transistor with its gate connected to its source or drain, a four-layer diode, an NPN transistor, and a PNP transistor.

11. An integrated circuit including the memory structure of claim 1.

12. A memory carrier including the memory structure of claim 1.

13. An electronic device configured to receive the memory carrier of claim 12.

14. An electronic device including the memory structure of claim 1.

15. The memory structure of claim 1 wherein:

said second electrode comprises a conductive tub; and

said edge comprises a rim of said conductive tub.

16. The memory structure of claim 1 wherein:

said second electrode comprises a truncated conductive cone; and

said edge comprises a rim of said truncated conductive cone.

17. The memory structure of claim 1 wherein:

said third electrode comprises a conductive pillar;

said second electrode comprises a conductor having an edge laterally adjacent said conductive pillar; and

a memory storage element disposed between said conductive pillar and said edge of said conductor.

18. The memory structure of claim 17 wherein said conductor comprises a conductive plate having an edge laterally adjacent said conductive pillar.

19. The memory structure of claim 1 wherein:

said third electrode comprises a conductive tub;

said second electrode comprises a conductor having an edge laterally adjacent said conductive tub; and

a memory storage element disposed between said conductive tub and said edge of said conductor.

20. The memory structure of claim 19 wherein said conductor comprises a conductive plate having an edge laterally adjacent said conductive tub.

21. The memory structure of claim 1 wherein:

said third electrode comprises a conductive structure having a vertical extent;

said second electrode comprises a non-horizontal conductive panel laterally adjacent said conductor and a horizontal conductive plate connected to said conductive panel;

said first electrode comprises a conductor laterally adjacent said conductive panel;

said memory storage element is disposed between an edge of said horizontal plate and said conductive structure; and

said control element is disposed between said conductor and said conductive panel.

22. The memory structure of claim 21 wherein said conductive structure comprises a conductive pillar.

23. The memory structure of claim 21 wherein said conductive structure comprises a conductive tub.

24. The memory structure of claim 21 wherein:

said conductor comprises an elongated conductive wall having a vertical extent;

said conductive panel is laminarly adjacent said elongated conductive wall; and

said control element is disposed between said conductive panel and said elongated conductive wall.

25. A memory structure comprising:

a conductive structure having a vertical extent;

a first conductor having an edge laterally adjacent said conductive structure;

a first memory storage element disposed between said conductive structure and said edge of said first conductor;

a second conductor having an edge laterally adjacent said conductive structure; and

a second memory storage element disposed between said conductive structure and said edge of said second conductor.

26. The memory structure of claim 25 wherein said conductive structure comprises a conductive pillar.

27. The memory structure of claim 25 wherein said conductive structure comprises a conductive tub.

28. A memory structure comprising:

a first electrode;

a second electrode having an edge;

a third electrode;

a memory tunnel junction region disposed between said third electrode and said edge of said second electrode; and

a control tunnel junction disposed between said second electrode and said first electrode.

29. The memory structure of claim 28 wherein said memory tunnel junction region comprises an oxide of said second electrode.

30. The memory structure of claim 28 wherein said memory storage element comprises an oxide different from an oxide of said second electrode.

31. The memory structure of claim 28 wherein said control tunnel junction region comprises an oxide of said first electrode.

32. The memory structure of claim 28 wherein said control tunnel junction region comprises an oxide different from an oxide of said first electrode.

33. The memory structure of claim 28 wherein said second electrode comprises a conductive tub having a rim edge.

34. The memory structure of claim 28 wherein said second electrode comprises a conductive plate having an edge.

35. The memory structure of claim 28 wherein said third electrode comprises a conductive tub.

36. The memory structure of claim 28 wherein said third electrode comprises a conductive pillar.

37. A memory structure comprising:

a first electrode;

a second electrode having an edge;

a third electrode;

means disposed between said third electrode and said edge of said second electrode for storing a memory state; and

means disposed between said second electrode and said first electrode for providing current to said means for storing.

38. A method of making a memory structure comprising:

creating a first electrode;

forming a control element on the first electrode;

creating a second electrode having an edge;

forming memory storage element on the second electrode; and

creating a third electrode in contact with the memory storage element.

39. The method of claim 38 wherein creating a second electrode having an edge comprises creating a conductive tub having a rim edge.

40. The method of claim 38 wherein creating a second electrode having an edge comprises creating a conductive plate having an edge.

41. A memory structure made in accordance with the method of claim 38.

42. A method of making a memory structure comprising:

creating a first electrode having an edge;

forming a memory storage element on the edge of the first electrode;

creating a second electrode in contact with the memory storage element;

forming a control element on the second electrode;

forming a third electrode in contact with the control element.

43. The method of claim 42 wherein creating a first electrode having an edge comprises creating a conductive truncated cone having a rim edge.

44. A memory structure made in accordance with the method of claim 42.