Integrated circuit device

• US 20030184339A1
• Filed: 05/16/2003
• Published: 10/02/2003
• Est. Priority Date: 05/24/2001
• Status: Active Grant

• Current Assignee: Fuji Xerox Company Limited (Xerox Holdings Corp.)
• Original Assignee: IP Flex Incorporated
• Inventors: Ikeda, Kenji, Shimura, Hiroshi, Sato, Tomoyoshi
• Granted Patent: US 7,191,312 B2
• Time in Patent Office: Days
• US Class Current: 326/47
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

An integrated circuit device with a data processing block is provided, the data processing block including a plurality of operation units that are arranged in a matrix, a plurality of first wire sets that extend in a first direction in the matrix and transfer input data of each operation unit, a plurality of second wire sets that extend in a second direction in the matrix and transfer output data of each operation unit, and a plurality of switching units that are arranged at each intersection between the first and second wire sets and can select and connect any wire in the first wire sets and any wire in the second wire sets. The plurality of operation units include a plurality of types of operation units with different data paths that are suited to special-purpose, processing, with an arrangement of operation units of the same type in the first direction or the second direction being formed in at least part of the data processing block. The functioning of the integrated circuit device can be dynamically changed by changing the configuration of the operation units and the integrated circuit device is composed of operation units with different data paths that are suited to special-purpose processing so that the integrated circuit device is both compact and economical.

Claims

1. An integrated circuit device, comprising a data processing block including:

a plurality of operation units that are arranged in a first and second direction in a matrix;

a plurality of first wire sets that extend in the first direction corresponding to an arrangement of the plurality of operation units in the first direction and transfer input data and/or output data of each of the operation units;

a plurality of second wire sets that extend in the second direction corresponding to an arrangement of the plurality of operation units in the second direction and transfer input data and/or output data of each of the operation units; and

a plurality of switching units that are positioned at each intersection between the first wire sets and the second wire sets and are capable of selecting and connecting any wire included in the first wire sets to any wire included in the second wire sets,

wherein the plurality of operation units are sorted into a plurality of types of operation units that include different data paths that are suited to special-purpose processing, and operation units of the same type form an arrangement in the first direction or the second direction in at least part of the data processing block.

2. An integrated circuit device according to claim 1,

wherein the plurality of types of operation units are arranged at equal intervals in the first direction.

3. An integrated circuit device according to claim 1,

wherein the plurality of types of operation units include different types of operation units that include data paths that are suited to at least one different processing of instruction level.

4. An integrated circuit device according to claim 1,

wherein the plurality of types of operation units include operation units that include data paths suited to processing for an input and/or output of data and are arranged at one end and other end of the data processing block.

5. An integrated circuit device according to claim 1,

wherein each of the plurality of types of operation units includes a flip-flop for latching input data and a flip-flop for latching output data.

6. An integrated circuit device according to claim 1,

wherein the plurality of types of operation units includes at least one type of operation units that include a path that links another operation units arranged in a same direction and provides an expanded operating function.

7. An integrated circuit device according to claim 1,

wherein each operation unit includes means for selecting wires included in the first wire sets and/or the second wire sets and inputting and/or outputting a signal.

8. An integrated circuit device according to claim 7,

wherein each operation unit includes a rewritable configuration memory that stores a selection of wires and each switching unit includes a rewritable configuration memory that stores a selection of wires.

9. An integrated circuit device according to claim 8,

wherein each operation unit includes means for changing and/or selecting part of an internal data path and the configuration memory stores a change and/or selection of the internal data path.

10. An integrated circuit device according to claim 9,

wherein the internal data path is suited to at least one processing of instruction level.

11. An integrated circuit device according to claim 8,

further comprising a general-purpose processor capable of rewriting the content of the configuration memory.

12. An integrated circuit device according to claim 1, further comprising a plurality of data processing blocks and a third wire set that connects the plurality of data processing blocks.

13. An integrated circuit device according to claim 1,

wherein each operation unit processes data in byte unit and/or in word unit.

14. An integrated circuit device according to claim 1,

wherein the first and second wire sets include bus wires for transferring data and carry wires for transferring carry signals.

15. An integrated circuit device according to claim 1,

wherein each operation unit includes means for inputting a signal from any of the wires included in the second wire sets and means for outputting a signal to any wire included in the first wire sets, and

the second wire sets include a pair of wire sets that extend on both sides of an arrangement of the plurality of operation units in the second direction.

16. An integrated circuit device according to claim 1,

wherein the data processing block includes a first matrix and a second matrix that are connected via an arrangement of operation units, out of the plurality of types of operation units, that include a data path suited to processing for delaying a transfer of data.

17. An integrated circuit device according to claim 1,

wherein the plurality of types of operation units include at least one of:

a first type of operation unit including a data path suited to input processing of data;

a second type of operation unit including a data path suited to processing that indicates an address of input data;

a third type of operation unit including a data path suited to output processing of data;

a fourth type of operation unit including a data path suited to processing that indicates an address of data to be outputted;

a fifth type of operation unit including a data path suited to processing for arithmetic operations and/or logic operations;

a sixth type of operation unit including a data path suited to multiplication processing;

a seventh type of operation unit including a data path suited to processing that delays a transfer time of data;

an eighth type of operation unit including a data path suited to processing that connects to a computational circuit located on an outside of the data processing block; and

a ninth type of operation unit including a data path whose processing is selected using a lookup table.

18. An integrated circuit device comprising a data processing block including a plurality of types of operation units and a wiring group for connecting the plurality of types of operation units,

wherein the plurality of types of operation units include different types of operation units that include data paths that are suited to execution of at least one different instruction.

19. An integrated circuit device according to claim 18,

wherein the plurality of types of operation units include at least one of:

a first type of operation unit including a data path suited to execution of an input instruction for data;

a second type of operation unit including a data path suited to execution of an instruction that indicates an address of input data;

a third type of operation unit including a data path suited to execution of an output instruction for data;

a fourth type of operation unit including a data path suited to execution of an instruction that indicates an address of data to be outputted;

a fifth type of operation unit including a data path suited to execution of an arithmetic operation instruction and/or a logic operation instruction; and

a sixth type of operation unit including a data path suited to execution of a multiplication instruction.

20. An integrated circuit device according to claim 19,

wherein the plurality of types of operation units further include at least one of:

a seventh type of operation unit including a data path suited to processing that delays a transfer time of data;

an eighth type of operation unit including a data path suited to processing that connects to a computational circuit located on an outside of the data processing block; and

a ninth type of operation unit including a data path whose processing is selected using a lookup table.

21. An integrated circuit device according to claim 18,

wherein each of the plurality of types of operation unit includes a flip-flop for latching input data and a flip-flop for latching output data.

22. An integrated circuit device according to claim 18,

wherein the plurality of types of operation units are arranged in a first and second direction in a matrix;

23. An integrated circuit device according to claim 22,

wherein the plurality of types of operation units include operation units that include data paths suited to execution of an input instruction and/or an output instruction for data and are arranged at one end and other end of the data processing block.

24. An integrated circuit device according to claim 22,

wherein the wiring group includes:

a plurality of first wire sets that extend in the first direction corresponding to an arrangement of the plurality of types of operation units in the first direction and transfer input data and/or output data of each of the operation units;

a plurality of second wire sets that extend in the second direction corresponding to an arrangement of the plurality of types of operation units in the second direction and transfer input data and/or output data of each of the operation units; and

a plurality of switching units that are arranged at each intersection between the first wire sets and the second wire sets and are capable of selecting and connecting any wire included in the first wire sets to any wire included in the second wire sets,

wherein each of the plurality of types of operation units includes means for selecting any of the wires included in the first wire sets and/or the second wire sets and inputting and/or outputting a signal.

25. An integrated circuit device according to claim 18,

wherein the wiring group changes a configuration of the plurality of types of operation units for data processing by changing a route of data supplied to the plurality of types of operation units.

26. An integrated circuit device according to claim 25,

wherein each of the plurality of types of operation unit includes a rewritable configuration memory that stores a selection of wires and the switching units each include a rewritable configuration memory that stores a selection of wires.

27. An integrated circuit device according to claim 26,

wherein the plurality of types of operation units include at least one type of operation units that include an internal data path that is suited to execution of at least one instruction and means for selecting and/or changing part of the internal data path,

and the configuration memory in the at least one type of operation units stores a selection and/or change of the internal data path.

28. An integrated circuit device according to claim 26,

further comprising a control unit for rewriting a content of the configuration memories based on a program.

29. An integrated circuit device according to claim 25,

further comprising a control unit for controlling a configuration of the plurality of types of operation units based on a program.

30. An integrated circuit device according to claim 29,

wherein the plurality of types of operation unit include at least one type of operation units that include an internal data path that is suited to execution of at least one instruction and means for selecting and/or changing part of the internal data path, and

the control unit also controls a selection and/or change of the internal data path.

31. An integrated circuit device according to claim 29,

wherein the control unit is a general-purpose processor.

32. An integrated circuit device according to claim 18,

further comprising a plurality of data processing blocks and another wiring group for connecting the plurality of data processing blocks.

33. An integrated circuit device comprising a data processing block including a plurality of operation units and a wiring group for connecting the plurality of operation units,

wherein the plurality of operation units are sorted into a plurality of types of operation units including different data paths that are suited to special-purpose processing, and each operation unit processes data in byte unit and/or in word unit.

34. An integrated circuit device according to claim 33,

wherein the plurality of types of operation units include different types of operation units that include data paths that are suited to at least one different processing of instruction level.

35. A method of designing an integrated circuit device that includes a data processing block composed of a plurality of types of operation units which are arranged in a first direction and a second direction in a matrix and a wiring group that connects the plurality of types of operation units, the plurality of types of operation units including different types of operation units that include data paths suited to processing of at least one different instruction,

the method of designing comprising steps of:

converting at least a part of processing that is executed in the integrated circuit device into an intermediate description written in a programming language including instructions that are executed by corresponding types of operation units of the plurality of types of operation unit;

generating an execution configuration of the plurality of types of operation units, the execution configuration being capable of executing processing of the intermediate description; and

generating the data processing block in which the plurality of types of operation units are arranged so as realize the execution configuration.

36. A method of designing according to claim 35,

wherein in the step of generating an execution configuration, in order to adjust timing, the execution configuration is generated including an operation unit that includes a data path suited to processing that delays a transfer time of data.

37. A method of designing an integrated circuit device that includes a data processing block in which a plurality of types of operation units are arranged and in which a configuration of the plurality of types of operation unit for data processing is changed by changing a route of data that is supplied to the plurality of types of operation units by a wiring group, the plurality of types of operation units including different types of operation units that include data paths suited to processing for at least one different instruction,

the method of designing comprising the steps of:

converting at least a part of processing that is executed in the integrated circuit device into an intermediate description written in a programming language that includes instructions that are executed by corresponding types of operation units of the plurality of types of operation units;

generating an execution configuration of the plurality of types of operation units, the execution configuration being capable of executing processing of the intermediate description;

generating the data processing block in which the plurality of types of operation unit that are required for the execution configuration are arranged; and

generating an execution program for the integrated circuit device, the execution program including an instruction that indicates the execution configuration.

38. A method of designing according to claim 37,

wherein at least one type of operation units of the plurality of types of operation units include an internal data path that is suited to processing of at least one instruction and means for selecting and/or changing part of the internal data path, and

in the step for generating an execution configuration, the execution configuration that also includes a selection and/or change of the internal data path is generated.

39. A method of generating an execution program for an integrated circuit device that includes a data processing block in which a plurality of types of operation units are arranged and in which a configuration of the plurality of types of operation unit for data processing is changed by changing a route of data that is supplied to the plurality of types of operation units by a wiring group, the plurality of types of operation units including different types of operation units that include data paths suited to processing for at least one different instruction,

the method of generating comprising the steps of:

converting at least a part of processing that is executed in the integrated circuit device into an intermediate description written in a programming language that includes instructions that are executed by corresponding types of operation units of the plurality of types of operation units;

generating an execution configuration of the plurality of types of operation units, the execution configuration being capable of executing processing of the intermediate description; and

generating the execution program that includes an instruction for indicating the execution configuration.

40. A method of generating according to claim 39,

wherein in the step of generating an execution configuration, in order to adjust timing of processing of an operation unit that includes a data path suited to a processing of an instruction, the execution configuration including an operation unit that includes a data path suited to processing that delays a transfer time of data is generated.

41. A method of generating according to claim 39,

wherein at least one of the plurality of operation units includes an internal data path that is suited to processing of at least one instruction and means for selecting and/or changing part of the internal data path, and

in the step for generating an execution configuration, the execution configuration that also includes a selection and/or change of the internal data path is generated.