Display controller provided with dynamic output clock

• US 20030184678A1
• Filed: 11/12/2002
• Published: 10/02/2003
• Est. Priority Date: 04/01/2002
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MStar Semiconductor Incorporated (MediaTek, Inc.)
• Inventors: Chen, Jiunn-Kuang, Hsiao, Wen-Ho, FanChiang, Hsu-Lin
• Granted Patent: US 7,202,870 B2
• Time in Patent Office: Days
• US Class Current: 348/511
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 5/003 Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto specific for a CRT G09G1/165; for a flat panel G09G3/2092
• CPC Class Codes: H04N 5/14 Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00

Abstract

The present invention provides a display controller for scaling an input source image. The display controller dynamically adjusts the output clock so line buffer requirement is reduced to a minimum to balance input and output image timing for image scaling or non-scaling to destination devices. The present invention supports up-scaling and down-scaling or bypass. The blocks of the line buffer operates in a continuous and cyclical manner according to the status signal generated by the line buffer status detector and the output clock. As a result, any buffer overrun or underrun condition will be immediately corrected by the timing and therefore the number of blocks of line buffer are greatly reduced.

Claims

1. A display controller, comprising:

a line buffer;

an input means for writing line data into said line buffer at an input line rate;

an output means for reading said written line data from said line buffer at an output line rate;

a status detector coupled to said input means and said output means for generating a status signal indicating whether said input line rate and said output line rate are unbalanced; and

a clock generator for dynamically adjusting said output line rate in response to said status signal until said input line rate and said output line rate reach balance.

2. The display controller as claimed in claim 1, wherein said clock generator dynamically tune the time period of an output clock responsive to said status signal so that said output line rate can be adjusted.

3. The display controller as claimed in claim 2, wherein said clock generator further comprises:

an oscillator for providing a reference signal;

a period control word generator for generating a period control signal in response to said status signal; and

a frequency synthesizer for generating said output clock in response to said reference signal and said period control signal.

4. The display controller as claimed in claim 1, wherein said line buffer comprises a plurality of blocks connected in the form of a ring.

5. The display controller as claimed in claim 1, wherein said status detector further comprises:

a write counter for identifying a write position when said input means writes into said line buffer;

a read counter for identifying a read position when said output means reads from said line buffer;

a position difference counter for generating a position difference signal in response to said write position and said read position; and

a judgment circuit for generating said status signal in response to said position difference signal.

6. A method for balancing an input line rate and an output line rate of a display controller comprising:

writing line data into a line buffer at said input line rate;

reading said written line data from said line buffer at said output line rate based upon an output clock;

detecting a write position currently writing into said line buffer and a read position currently reading said line buffer;

generating a position difference signal in response to said write position and said read position;

generating a status signal in response to said position difference signal; and

dynamically tuning the time period of said output clock and thus adjusting said output line rate in response to said status signal until said input line rate and said output line rate reach balanced.