Power distribution circuitry including control unit IC

• US 20030184934A1
• Filed: 04/01/2002
• Published: 10/02/2003
• Est. Priority Date: 04/01/2002
• Status: Abandoned Application

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Paullin, Andrew Rhodes, Bushue, Michael J.
• Application Number:
  US10/112,898
• Publication Number:
  US 20030184934A1
• Time in Patent Office: Days
• US Class Current: 361/62
• CPC Class Codes: H02J 1/10 Parallel operation of dc sources

Abstract

A power distribution circuit is disclosed. In one embodiment, the power distribution circuit includes a plurality of transistors and a control unit IC. First terminals of each of the transistors may be coupled to separate voltage sources. Second terminals of each of the transistors may be coupled to a common power node. An electronic system may receive power from one of the voltage sources when one of the transistors is on. The control unit IC may activate one or more of the transistors by driving a voltage to the control terminal of the transistor to be activated. The control unit IC may also monitor a voltage difference between the first terminal and the second terminal of each of the transistors. If the voltage of the second terminal becomes greater than the voltage of the first terminal for a given transistor, the control terminal may deactivate the transistor.

Claims

1. A power distribution circuit comprising:

a control unit IC (integrated circuit); and

a plurality of transistors, wherein each of the plurality of transistors includes a first terminal, a second terminal, and a control terminal, wherein the control terminal of each of the plurality of transistors is coupled to the control unit IC, wherein the first terminal of each of the plurality of transistors is coupled to a power source, and wherein the second terminal of each of the plurality of transistors is coupled to a power node for supplying power to an electronic system;

wherein the control unit IC is configured to activate at least one of the plurality of transistors by driving a bias voltage onto the control terminal of the at least one transistor, and wherein the control unit IC is configured to monitor a voltage difference between the first terminal and the second terminal.

2. The power distribution circuit as recited in claim 1, wherein the control unit IC is mounted in a surface mount package.

3. The power distribution circuit as recited in claim 1, wherein the first terminal and the second terminal of each of the plurality of transistors is coupled to the control unit IC.

4. The power distribution circuit as recited in claim 3, wherein the control unit IC includes a voltage detection circuit, and wherein the voltage difference between the first terminal and the second terminal of each of the plurality of transistors is monitored by the voltage detection circuit.

5. The power distribution circuit as recited in claim 4, wherein the control unit IC is configured to de-activate the one of the plurality of transistors responsive to the voltage detection circuit detecting that the voltage magnitude on the first terminal is less than the voltage on the second terminal.

6. The power distribution circuit as recited in claim 3, wherein the voltage detection circuit is a comparator.

7. The power distribution circuit as recited in claim 6, wherein the comparator is an analog comparator.

8. The power distribution circuit as recited in claim 1, wherein the control unit IC includes a biasing circuit, and wherein the biasing circuit is configured to apply a bias voltage to the control terminal of each of the plurality of transistors.

9. The power distribution circuit as recited in claim 8, wherein the biasing circuit is a charge pump.

10. The power distribution circuit as recited in claim 1, wherein each of the plurality of transistors is a field effect transistor (FET), wherein the first terminal of each transistor is a source terminal, the second terminal of each transistor is a drain terminal, and the control terminal of each transistor is a gate terminal.

11. A method for distributing power to an electronic circuit, the method comprising:

providing a plurality of power sources;

providing a control unit IC (integrated circuit); and

providing a plurality of transistors, wherein each of the transistors includes a first terminal, a second terminal, and a control terminal, wherein the first terminal of each of the plurality of transistors is coupled to one of the plurality of power sources, wherein the second terminal of each of the plurality of transistors is coupled to a power node of an electronic circuit, and wherein the control terminal of each of the plurality of transistors is coupled to the control unit IC, wherein the control unit IC is configured to activate one of the plurality of transistors by driving a bias voltage onto the control terminal of the one of the plurality of transistors, and wherein the control unit IC is configured to monitor a voltage difference between the first terminal and the second terminal of the one of the plurality of transistors.

12. The method as recited in claim 11, wherein the control unit IC is mounted in a surface mount package.

13. The method as recited in claim 11 further comprising the control unit IC de-activating the one of the plurality of transistors responsive to detecting that the voltage magnitude on the first terminal of the one of the plurality of transistors is less than the voltage on the second terminal of the one of the plurality of transistors.

14. The method as recited in claim 13, wherein the voltage difference between the first terminal and the second terminal is monitored by a voltage detection circuit.

15. The method as recited in claim 14, wherein the voltage detection circuit is a comparator.

16. The method as recited in claim 15, wherein the comparator is an analog comparator.

17. The method as recited in claim 11, wherein the control unit IC includes a biasing circuit, and wherein the biasing circuit is configured to apply a bias voltage to the control terminal of each of the plurality of transistors.

18. The method as recited in claim 17, wherein the biasing circuit is a charge pump.

19. The method as recited in claim 11, wherein each of the plurality of transistors is a field effect transistor (FET), and wherein the first terminal of each of the plurality of transistors is a source terminal, the second terminal of each of the plurality of transistors is a drain terminal, and the control terminal of each of the plurality of transistors is a gate terminal.

20. A power control unit IC (integrated circuit) comprising:

a plurality of voltage detection circuits, wherein each of the voltage detection circuits is configured to detect a voltage difference between a first transistor terminal and a second transistor terminal;

a plurality of biasing circuits, wherein each of the plurality of biasing circuits is coupled to one of the plurality of voltage detection circuits; and

a plurality of switches, wherein each of the plurality of switches, when closed, is configured to allow a bias voltage from one of the plurality of biasing circuits to be driven onto a transistor control terminal, and wherein each of the plurality of voltage detection circuits is configured to cause an associated one of the plurality of switches to open responsive to detecting that the voltage magnitude on an associated first transistor terminal is less than the voltage magnitude on an associated second transistor terminal.

21. The power control unit IC as recited in claim 20, wherein the power control unit IC is mounted in a surface mount package.

22. The power control unit IC as recited in claim 20, wherein each of the plurality of voltage detection circuits is a comparator.

23. The power control unit IC as recited in claim 22, wherein the comparator is an analog comparator.

24. The power control unit IC as recited in claim 20, wherein the biasing circuit is a charge pump.

25. The power control unit IC as recited in claim 20, wherein the first transistor terminal is a source terminal, the second transistor terminal is a drain terminal, and the control terminal is a gate terminal.