Digital image processor

• US 20030185455A1
• Filed: 01/27/2003
• Published: 10/02/2003
• Est. Priority Date: 02/04/1999
• Status: Abandoned Application

• Current Assignee: Quvis
• Original Assignee: Quvis
• Inventors: Goertzen, Kenbe D.
• Application Number:
  US10/352,375
• Publication Number:
  US 20030185455A1
• Time in Patent Office: Days
• US Class Current: 382/240
• CPC Class Codes: H04N 19/10 using adaptive coding
• CPC Class Codes: H04N 19/112 according to a given display mode, e.g. for interlaced or progressive display mode
• CPC Class Codes: H04N 19/122 Selection of transform size, e.g. 8x8 or 2x4x8 DCT; Selection of sub-band transforms of varying structure or type
• CPC Class Codes: H04N 19/124 Quantisation
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/152 by measuring the fullness of the transmission buffer
• CPC Class Codes: H04N 19/154 Measured or subjectively estimated visual quality after decoding, e.g. measurement of distortion use of rate-distortion criteria H04N19/147
• CPC Class Codes: H04N 19/162 User input
• CPC Class Codes: H04N 19/174 the region being a slice, e.g. a line of blocks or a group of blocks
• CPC Class Codes: H04N 19/1883 the unit relating to sub-band structure, e.g. hierarchical level, directional tree, e.g. low-high [LH], high-low [HL], high-high [HH]
• CPC Class Codes: H04N 19/192 the adaptation method, adaptation tool or adaptation type being iterative or recursive
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/46 Embedding additional information in the video signal during the compression process H04N19/517, H04N19/68, H04N19/70 take precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/62 by frequency transforming in three dimensions H04N19/63 takes precedence
• CPC Class Codes: H04N 19/63 using sub-band based transform, e.g. wavelets
• CPC Class Codes: H04N 19/70 characterised by syntax aspects related to video coding, e.g. related to compression standards

Abstract

An electronic chip for processing a digital image stream having digital data values representing pixels and resulting digital signal. The electronic chip includes a compression module for compressing the digital image stream so that upon decompression the digital image stream maintains a pre-determined signal to noise ratio for each digital data value. The compression module may compress the digital image stream such that digital data values are quantized so as to maintain a desired resolution over all frequencies. The electronic chip may further include a digital image input port for receiving the digital image stream and a digital data output port for outputting the digital data stream formatted as a digital data packet.

Claims

1. An electronic chip for processing a digital image stream having digital data values representing a pixels, the electronic chip comprising:

a compression module for compressing the digital image stream so that upon decompression the digital image stream maintains a pre-determined signal to noise ratio for each digital data value.

3. The electronic chip according to claim 1 further comprising:

a digital image input port for receiving the digital image stream.

4. The electronic chip according to claim 1 further comprising:

a digital data output port for outputting the digital data stream formatted as a digital data packet.

5. The electronic chip according to claim 1, further comprising:

an interlaced module for converting a digital image stream from an interlaced format to a progressive format.

6. The electronic chip according to claim 1, further comprising:

an interlace module for decorrelating both spatially and temporally each pair of fields representing a frame.

7. The electronic chip according to claim 1, further comprising an encryption module for encrypting the digital image stream.

8. The electronic chip according to claim 1, wherein the compression module is configured to perform wavelet-based transforms.

9. The electronic chip according to claim 1, wherein the compression module includes

a spatial transform module wherein the spatial transform module is capable of employing a wavelet transform to decorrelate each image within the digital image stream into a plurality of frequency bands.

10. The electronic chip according to claim 1, wherein the compression module includes:

a temporal transform module capable performing a temporal decorrelation using a wavelet transform on the digital image stream to transform the digital image stream into a plurality of frequency bands.

11. The electronic chip according to claim 9, wherein the compression module includes:

a quantization module for assigning a quantization level to each defined frequency bard according to sampling theory.

12. The electronic chip according to claim 9, wherein the quantization module includes

circuitry for quantizing each transformed digital data value so that each transformed digital data value has the proper resolution for maintaining a desired quality level over all digital data values in the digital image stream.

13. The electronic chip according to claim 12, further comprising an entropy encoder.

14. The-electronic chip according to claim 13, wherein the entropy encoder includes circuitry for selecting a probability distribution function based upon a characteristic of the digital image stream.

15. The electronic chip according to claim 12, wherein the quantization module includes circuitry for assigning quantization levels with greater accuracy to each frequency band of lower frequency.

16. The electronic chip according to claim 3, wherein the digital data output port has circuitry for adding a header to the digital data packet, wherein the header at least indicates size.

17. The electronic chip according to claim 16, wherein the size header indicates the size of the original digital image stream.

18. The electronic chip according to claim 1, wherein the compression module performs compression of the digital image stream in real-time.

19. The electronic chip according to claim 1, wherein the digital image stream is streaming media.

20. The electronic chip according to claim 3, wherein the digital data packet contains an encrypted data from the digital image stream.

21. The electronic chip according to claim 3, wherein the digital data output port adds a block boundary aligner to the header.

22. The electronic chip according to claim 3, wherein the digital data output produces a digital data packet that contains an entropy encoded data packet with a header field and a size field.

23. The electronic chip according to claim 22, wherein the header field may contain entropy parameters.

24. The electronic chip according to claim 23, wherein the entropy parameters may include signal to noise ratio, core magnitude, dither magnitude and dither seed.

55. The electronic chip according to claim 16, wherein the size header indicates the size of the original digital image stream.

2. An electronic chip for processing a digital image stream having digital data values, the electronic chip comprising:

a compression module for compressing the digital image stream wherein digital data values are quantized so as to maintain a desired resolution over all frequencies.

25. Digital data on a carrier wave, the digital data comprising:

compressed digital data that upon decompression maintains at least a predetermined signal to noise ratio over all digital data values.

26. The digital data according to claim 25, wherein the digital data further includes an appended header.

27. The digital data according to claim 26, wherein the header indicates the size of the digital data that is compressed.

28. The digital data according to claim 26, wherein the header indicates the size of the digital data prior to being compressed.

29. The digital data according to claim 25, wherein the compressed digital data is encrypted.

30. The digital data according to claim 25 wherein the digital data upon decompression includes a header which indicates the pre-determined quality level.

31. An electronic chip for processing digital video, the system comprising:

a digital image input for receiving a digital image stream;

a wavelet-based compression module capable of compressing the digital image stream maintaining a predetermined quality level over all frequencies within the digital image stream;

a digital data output for outputing a digital data stream having the format of a digital data packet.

32. The electronic chip according to claim 31, further comprising:

an interlaced-module for converting a digital image stream from an interlaced format to a progressive format.

33. The electronic chip according to claim 32, wherein the interlaced processor decorrelates each pair of fields representing a frame both spatially and temporally.

34. The electronic chip according to claim 31, further comprising an encryption module for encrypting the digital image stream.

35. The electronic chip according to claim 31, wherein the wavelet-based compression module includes:

a spatial transform module wherein the spatial transform module is capable of employing a wavelet transform to decorrelate each frame of video within the digital image stream into a plurality of frequency bands.

36. The electronic chip according to claim 35, wherein the wavelet-based compression module includes:

a temporal transform module capable performing a temporal decorrelation using a wavelet transform on the digital image stream to transform the digital image stream into a plurality of frequency bands.

37. The electronic chip according to claim 36, further comprising:

a quantization module for assigning a quantization level to each defined frequency band.

38. The electronic chip according to claim 37, further comprising an entropy encoder.

39. The electronic chip according to claim 37, wherein the quantization module assigns quantization levels with greater accuracy to each frequency band of a lower octave.

40. A digital data packet on a carrier wave, the digital data packet comprising:

digital data that is compressed using a wavelet based transform maintaining a pre-determined quality level over all frequencies of the digital data.

41. An electronic chip for processing a digital image stream having digital data values representing a pixels, the electronic chip comprising:

means for compressing the digital image stream so that upon decompression the digital image stream maintains a pre-determined signal to noise ratio for each digital data value.

43. The electronic chip according to claim 41 further comprising:

means for receiving the digital image stream.

44. The electronic chip according to claim 41 further comprising:

means for outputting the digital data stream formatted as a digital data packet.

45. The electronic chip according to claim 41, further comprising:

means for converting a digital image stream from an interlaced format to a progressive format.

46. The electronic chip according to claim 41, further comprising:

means for decorrelating both spatially and temporally each pair of fields representing a frame.

47. The electronic chip according to claim 41, further comprising an means for encrypting the digital image stream.

48. The electronic chip according to claim 41, wherein the means for compressing is configured to perform wavelet-based transforms.

49. The electronic chip according to claim 41, wherein the means for compressing includes

means for employing a wavelet transform to decorrelate each image within the digital image stream into a plurality of frequency bands.

50. The electronic chip according to claim 41, wherein the means for compressing includes:

means for performing a temporal decorrelation using a wavelet transform on the digital image stream to transform the digital image stream into a plurality of frequency bands.

51. The electronic chip according to claim 49, wherein the means for compressing includes:

means for assigning a quantization level to each defined frequency band according to sampling theory.

52. The electronic chip according to claim 49, further comprising:

means for quantizing each transformed digital data value so that each transformed digital data value has the proper resolution for maintaining a desired quality level over all digital data values in the digital image stream.

53. The electronic chip according to claim 52, further comprising means for entropy encoding.

54. The electronic chip according to claim 44, wherein the means for outputting includes means for adding a header to the digital data packet, wherein the header at least indicates size.

57. The digital data sequence on a processor readable medium according to claim 46, wherein the digital data further includes an appended header.

58. The digital data sequence on a processor readable medium according to claim 57, wherein the header indicates the size of the digital data that is compressed.

59. The digital data sequence on a processor readable medium according to claim 57, wherein the header indicates the size of the digital data prior to being compressed.

42. An electronic chip for processing a digital image stream having digital data values, the electronic chip comprising:

means for compressing the digital image stream wherein digital data values are quantized so as to maintain a desired resolution over all frequencies.

56. A digital data sequence on a processor-readable medium, the digital data sequence on the processor-readable medium comprising:

compressed digital data that upon decompression maintains at least a pre-determined signal to noise ratio over all digital data values.

60. The digital data sequence on a processor readable medium according to claim 56, wherein the compressed digital data is encrypted.

61. The digital data sequence on a processor readable medium according to claim 56 wherein the digital data upon decompression includes a header which indicates the predetermined quality level.