Method and circuit or down-converting a signal

• US 20030186670A1
• Filed: 03/24/2003
• Published: 10/02/2003
• Est. Priority Date: 10/21/1998
• Status: Active Grant

• Current Assignee: ParkerVision, Inc.
• Original Assignee: ParkerVision, Inc.
• Inventors: Cook, Robert W., Rawlins, Gregory S., Bultman, Michael J., Sorrells, David F., Moses, Charley D. Jr., Looke, Richard C., Rawlins, Michael W.
• Granted Patent: US 7,389,100 B2
• Time in Patent Office: Days
• US Class Current: 455/323
• CPC Class Codes: H03C 1/62 Modulators in which amplitude of carrier component in output is dependent upon strength of modulating signal, e.g. no carrier output when no modulating signal is present H03C1/28 - H03C1/34, H03C1/46, H03C1/48 take precedence
• CPC Class Codes: H03D 7/00 Transference of modulation from one carrier to another, e.g. frequency-changing H03D9/00, H03D11/00 take precedence; dielectric amplifiers, magnetic amplifiers, parametric amplifiers used as a frequency-changers H03F
• CPC Class Codes: H03D 7/1441 using field-effect transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1475 Subharmonic mixer arrangements
• CPC Class Codes: H04B 1/0025 using a sampling rate lower than twice the highest frequency component of the sampled signal for demodulation of angle-modulated signals H03D3/006
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 7/12 Frequency diversity
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 27/00 Modulated-carrier systems
• CPC Class Codes: H04L 27/06 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/12 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/148 using filters, including PLL-type filters
• CPC Class Codes: H04L 27/156 with demodulation using temporal properties of the received signal, e.g. detecting pulse width
• CPC Class Codes: H04L 27/2672 Frequency domain
• CPC Class Codes: H04L 27/3881 using sampling and digital processing, not including digital systems which imitate heterodyne or homodyne demodulation

Abstract

Methods, systems, and apparatuses for down-converting an electromagnetic (EM) signal by aliasing the EM signal are described herein. Briefly stated, such methods, systems, and apparatuses operate by receiving an EM signal and an aliasing signal having an aliasing rate. The EM signal is aliased according to the aliasing signal to down-convert the EM signal. The term aliasing, as used herein, refers to both down-converting an EM signal by under-sampling the EM signal at an aliasing rate, and down-converting an EM signal by transferring energy from the EM signal at the aliasing rate. In an embodiment, the EM signal is down-converted to an intermediate frequency (IF) signal. In another embodiment, the EM signal is down-converted to a demodulated baseband information signal. In another embodiment, the EM signal is a frequency modulated (FM) signal, which is down-converted to a non-FM signal, such as a phase modulated (PM) signal or an amplitude modulated (AM) signal.

Claims

1. A direct-conversion frequency converter, comprising:

a complimentary field-effect-transistor-based switch module; and

a bias network coupled to an input node of said complimentary field-effect-transistor-based switch module, wherein the bias network biases the input node to a voltage that is between a first voltage and a second voltage.

2. The apparatus according to claim 1, wherein said first voltage is a positive voltage and said second voltage is ground.

3. The apparatus according to claim 1, wherein said first voltage is a positive voltage and said second voltage is a negative voltage.

4. The apparatus according to claim 1, wherein said bias network comprises:

a first resistance coupled between said input node and said first voltage; and

a second resistance coupled between said input node and said second voltage.

5. The apparatus according to claim 4, wherein said first voltage is a positive voltage and said second voltage is ground.

6. The apparatus according to claim 4, wherein said first voltage is a positive voltage and said second voltage is a negative voltage.

7. A clock splitter circuit for a in-phase and quadrature-phase direct-conversion frequency converter, comprising:

an input terminal;

an in-phase output terminal;

a quadrature-phase output terminal;

an in-phase path including an odd number of series-coupled inverters and a first flip-flop, coupled between the input terminal and the in-phase output terminal; and

a quadrature-phase path including an even number of series-coupled inverters and a second flip-flop, coupled between the input terminal and the quadrature-phase output terminal;

wherein the in-phase path and the quadrature-phase path output in-phase and quadrature phase control signals, respectivley, that are substantially ninety degrees out of phase with one another.

8. The apparatus according to claim 7, wherein the in-phase path includes three series-coupled inverters, and the quadrature-phase path includes two series-coupled inverters.

9. The apparatus according to claim 7, wherein each of the inverters comprises:

an N-type transistor including drain, source, and gate terminals; and

and a P-type transistor including drain, source, and gate terminals;

wherein the N-type transistor gate terminal and the P-type transistor gate terminals are coupled to one another and serve as an input terminal to the respective inverter;

wherein the N-type transistor drain terminal and the P-type transistor drain terminals are coupled to one another and serve as an output terminal of the respective inverter;

wherein the P-type transistor source terminal is coupled to a relatively low voltage source;

wherein the N-type transistor source terminal is coupled to a relatively high voltage source.

10. The apparatus according to claim 7, wherein the in-phase and quadrature-phase direct-conversion frequency converter comprises:

an in-phase direct-conversion frequency converter path including an in-phase switch module controlled by the in-phase control signal; and

a quadrature-phase direct-conversion frequency converter path including a quadrature-phase switch module controlled by the quadrature-phase control signal.

11. An in-phase and quadrature-phase direct-conversion frequency converter, comprising:

an in-phase direct-conversion frequency converter path;

a quadrature-phase direct-conversion frequency converter path; and

a clock splitter circuit that provides an in-phase control signal to the in-phase direct-conversion frequency converter path and a quadrature-phase control signal to the quadrature-phase direct-conversion frequency converter path, wherein the in-phase control signal and the quadrature-phase control signal are substantially ninety degrees out of phase with one another.

12. The apparatus according to claim 11, wherein the clock splitter circuit comprises:

an input terminal coupled to a clock source;

an in-phase output terminal coupled to the in-phase direct-conversion frequency converter path;

a quadrature-phase output terminal coupled to the quadrature-phase direct-conversion frequency converter path;

an in-phase path including an odd number of series-coupled inverters and a first flip-flop, coupled between the input terminal and the in-phase output terminal; and

a quadrature-phase path including an even number of series-coupled inverters and a second flip-flop, coupled between the input terminal and the quadrature-phase output terminal.

13. The apparatus according to claim 12, wherein the in-phase path includes three series-coupled inverters, and the quadrature-phase path includes two series-coupled inverters.

14. The apparatus according to claim 12, wherein each of the inverters comprises:

an N-type transistor including drain, source, and gate terminals; and

and a P-type transistor including drain, source, and gate terminals;

wherein the N-type transistor gate terminal and the P-type transistor gate terminals are coupled to one another and serve as an input terminal to the respective inverter;

wherein the N-type transistor drain terminal and the P-type transistor drain terminals are coupled to one another and serve as an output terminal of the respective inverter;

wherein the P-type transistor source terminal is coupled to a relatively low voltage source;

wherein the N-type transistor source terminal is coupled to a relatively high voltage source.

15. The apparatus according to claim 11, wherein the in-phase direct-conversion frequency converter path comprises an in-phase switch module controlled by the in-phase control signal, and wherein the quadrature-phase direct-conversion frequency converter path comprises a quadrature-phase switch module controlled by the quadrature -phase control signal.

16. A direct-conversion frequency converter, comprising:

a switch module, including a plurality of switches coupled in parallel; and

a pulse generating circuit including an output coupled to a control input of the switch module.

17. The apparatus according to claim 16, wherein at least one of the plurality of switches includes an area under a gate portion between source and drain region that is sized to provide substantially sharp turn-on and turn-off characteristics for the switch module.

18. The apparatus according to claim 16, wherein at least one of the plurality of switches includes an area under a gate portion between source and drain region that is sized to provide substantially low resistance for the switch module during a turn-on time.

19. The apparatus according to claim 16, wherein a first set of at least one of the plurality of switches includes a first area under a gate portion between source and drain region, and a second set of at least one of the plurality of switches includes a second area under a gate portion between source and drain region, wherein the first area is larger than the second area, wherein the first area provides substantially sharp turn-on and turn-off characteristics for the switch module, wherein the second area provides substantially low resistance for the switch module during a turn-on time.

20. The apparatus according to claim 16, wherein the switch module comprises a plurality of field effect transistor-based switches.

21. The apparatus according to claim 16, wherein the switch module comprises a plurality of bi-polar switches.

22. The apparatus according to claim 16, wherein the switch module comprises a plurality of metal-oxide field effect transistor-based switches.

23. The apparatus according to claim 16, wherein the switch module comprises a plurality of junction field effect transistor-based switches.

24. The apparatus according to claim 16, wherein the switch module comprises a plurality of gallium-arsenide field effect transistor-based switches.

25. The apparatus according to claim 16, wherein the switch module comprises at least two of the following types of switches:

field effect transistor-based switches;

bi-polar switches;

metal-oxide field effect transistor-based switches;

junction field effect transistor-based switches; and

galium-arsenide field effect transistor-based switches.

26. The apparatus according to claim 20, wherein the plurality of field effect transistor-based switches comprises field effect transistor-based switches having similar characteristics.

27. The apparatus according to claim 20, wherein the plurality of field effect transistor-based switches comprises field effect transistor-based switches having different characteristics.

28. The apparatus according to claim 27, wherein the plurality of field effect transistor-based switches comprises field effect transistor-based switches having different areas under a gate portion between source and drain regions.

29. The apparatus according to claim 28, wherein at least one of the plurality of field effect transistor-based switches includes an area under a gate portion between source and drain region that is sized to provide substantially sharp turn-on and turn-off characteristics for the switch module.

30. The apparatus according to claim 28, wherein at least one of the plurality of field effect transistor-based switches includes an area under a gate portion between source and drain region that is sized to provide substantially low resistance for the switch module during a turn-on time.

31. The apparatus according to claim 28, wherein a first set of at least one of the plurality of field effect transistor-based switches includes a first area under a gate portion between source and drain region, and a second set of at least one of the plurality of field effect transistor-based switches includes a second area under a gate portion between source and drain region, wherein the first area is larger than the second area, wherein the first area provides substantially sharp turn-on and turn-off characteristics for the switch module, wherein the second area provides substantially low resistance for the switch module during a turn-on time.

32. The apparatus according to claim 16, wherein the plurality of switches coupled in parallel comprise:

a plurality of series-coupled n-channel metal oxide semiconductor transistors; and

a plurality of series-coupled p-channel metal oxide semiconductor transistors;

wherein the n-channel metal oxide semiconductor transistors are coupled in parallel with the p-channel metal oxide semiconductor transistors, in a complementary circuit configuration.

33. The apparatus according to claim 32, wherein the complementary circuit configuration permits the n-channel metal oxide semiconductor transistors to turn-on when an input signal falls and permits the p-channel metal oxide semiconductor transistors to turn-on when the input signal rises.

34. The apparatus according to claim 32, wherein the n-channel and p-channel metal oxide semiconductor transistors are sized to minimize effects of charge injection.

35. The apparatus according to claim 34, wherein lengths and widths of semiconductor traces of n-channel and p-channel metal oxide semiconductor transistors are sized to minimize effects of charge injection.

36. A direct-conversion frequency converter, comprising:

a switch module; and

a pulse generating circuit including an output coupled to a control input of the switch module, the pulse generating circuit including an aperture duration control circuit.

37. The apparatus according to claim 36, wherein the aperture control circuit comprises a voltage variable capacitor.

38. The apparatus according to claim 36, wherein the aperture duration control circuit comprises a real-time aperture duration control circuit.

39. The apparatus according to claim 38, wherein the pulse generating circuit further comprises a delay element in parallel with the real-time aperture control circuit.

40. The apparatus according to claim 38, wherein the real-time aperture control circuit comprises a resistor/capacitor network.

41. The apparatus according to claim 38, wherein the real-time aperture control circuit comprises a voltage variable capacitor.

42. A method of controlling a direct-conversion frequency converter that includes a switch module, comprising:

(1) generating a train of pulses from a clock signal;

(2) controlling the switch module with the train of pulses; and

(3) controlling apertures of the train of pulses to affect a characteristic of the direct-conversion frequency converter.

43. The method according to claim 42, wherein step (3) comprises controlling a ratio of a time that the switch module conducts to a time that the switch module does not conduct.

44. The method according to claim 42, wherein step (3) comprises controlling apertures of the train of pulses to affect an impedance characteristic of the direct-conversion frequency converter.

45. The method according to claim 42, wherein step (3) comprises controlling apertures of the train of pulses to affect an input impedance characteristic of the direct-conversion frequency converter.

46. The method according to claim 42 wherein step (3) comprises controlling apertures of the train of pulses to affect an output impedance characteristic of the direct-conversion frequency converter.

47. The method according to claim 42, wherein step (3) comprises controlling apertures of the train of pulses to affect input impedance and output impedance characteristics of the direct-conversion frequency converter.

48. The method according to claim 42, wherein step (3) comprises adjusting apertures of the train of pulses in real-time to affect a characteristic of the direct-conversion frequency converter.

49. The method according to claim 48, wherein step (3) comprises adjusting apertures of the train of pulses in real-time to affect an energy characteristic of the direct-conversion frequency converter.

50. The method according to claim 49, wherein step (3) comprises adjusting apertures of the train of pulses in real-time to optimize the energy transfer characteristic of the direct-conversion frequency converter.

51. The method according to claim 48, wherein step (3) comprises adjusting apertures of the train of pulses in real-time to affect a gain characteristic of the direct-conversion frequency converter.

52. The method according to claim 51, wherein step (3) comprises adjusting apertures of the train of pulses in real-time to optimize the gain characteristic of the direct-conversion frequency converter.