Method for verifying clock signal frequency of computer sound interface

• US 20030188053A1
• Filed: 04/01/2002
• Published: 10/02/2003
• Est. Priority Date: 04/01/2002
• Status: Active Grant

• Current Assignee: MiTAC International Corporation (MiTAC Holdings Corp.)
• Original Assignee: MiTAC International Corporation (MiTAC Holdings Corp.)
• Inventors: Tsai, Chun-Nan
• Granted Patent: US 6,898,723 B2
• Time in Patent Office: Days
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A method for verifying clock signal frequency of a sound interface of a computer system is disclosed. The processes include steps of initializing and setting a DMA controller and the sound interface, starting DMA data transfer, resetting a time out counter. During the DMA data transfer, a step of incrementing the time out counter is performed until the selected DMA channel of the DMA controller reaches a terminal count condition. After each increment, it is checked if DMA data transfer is time out. When the DMA channel of the DMA controller reaches the terminal count condition, the current count of the time out counter is compared with a maximum tolerable count and a minimum tolerable count. If the count of the time out counter is between the maximum and minimum tolerable counts, a message indicating the clock signal frequency of the sound interface is correct is issued, otherwise a message indicating the clock signal frequency is incorrect is issued.

Claims

1. A method for verifying a clock signal frequency of a sound interface installed in a computer system, the computer system comprises a main memory for storing sound data, a Direct Memory Access (DMA) controller having at least one DMA channel for performing a DMA data transfer which transfers the sound data from the main memory to the sound interface, a status register having a terminal count bit, and a clock signal generator for supplying a clock signal to the sound interface, the method comprising the following steps:

(a) initializing and setting the Direct Memory Access controller of the computer system and the sound interface to start the DMA data transfer;

(b) resetting a time out counter;

(c) incrementing the time out counter to get a current count during the DMA data transfer;

(d) checking whether the DMA channel of the Direct Memory Access controller reaches a terminal count condition by checking the terminal count bit of the status register of the Direct Memory Access controller;

(e) if negative in step (d), further checking if the DMA data transfer is time out, and going back to step (c) if it is not time out, otherwise issuing a time out message if it is time out; and

(f) if positive in step (d), further checking if the current count recorded in the time out counter is between a maximum tolerable count and a minimum tolerable count, and issuing a message indicating the clock signal frequency is correct if the current count is between the maximum tolerable count and the minimum tolerable count, otherwise issuing a message indicating the clock signal frequency is incorrect if the current count is not between the maximum tolerable count and the minimum tolerable count.

2. The method as claimed in claim 1, wherein the step (a) comprises the following steps:

(a1) enabling and resetting the Direct Memory Access controller;

(a2) initializing and setting the sound interface;

(a3) setting a DMA sampling count of the sound interface;

(a4) selecting a DMA channel and setting a DMA data transfer mode to the Direct Memory Access controller, and then setting a base address in a base address register and setting a byte count in a base byte counter of the Direct Memory Access controller;

(a5) enabling the DMA data transfer of the sound interface; and

(a6) unmasking the DMA channel of the Direct Memory Access controller to start the DMA data transfer.

3. The method as claimed in claim 2, wherein the step (a2) further comprises a step of setting a sampling rate and a data format to the sound interface.

4. The method as claimed in claim 1, wherein the maximum tolerable count and the minimum tolerable count of step (f) are determined in accordance with a tolerable clock jitter of the clock signal and a bus latency of the computer system.