Risc processor supporting one or more uninterruptible co-processors

• US 20030188127A1
• Filed: 04/01/2002
• Published: 10/02/2003
• Est. Priority Date: 04/01/2002
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: So, Kimming
• Granted Patent: US 6,944,746 B2
• Time in Patent Office: Days
• US Class Current: 712/34
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: H04N 19/12 Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
• CPC Class Codes: H04N 19/122 Selection of transform size, e.g. 8x8 or 2x4x8 DCT; Selection of sub-band transforms of varying structure or type
• CPC Class Codes: H04N 19/129 Scanning of coding units, e.g. zig-zag scan of transform coefficients or flexible macroblock ordering [FMO]
• CPC Class Codes: H04N 19/157 Assigned coding mode, i.e. the coding mode being predefined or preselected to be further used for selection of another element or parameter
• CPC Class Codes: H04N 19/176 the region being a block, e.g. a macroblock
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/60 using transform coding
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/70 characterised by syntax aspects related to video coding, e.g. related to compression standards
• CPC Class Codes: H04N 19/82 involving filtering within a prediction loop
• CPC Class Codes: H04N 19/90 using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals

Abstract

A system and method for processing instructions in a computer system comprising a processor and a co-processor communicatively coupled to the processor. Instructions are processed in the processor in an instruction pipeline. In the instruction pipeline, instructions are processed sequentially by an instruction fetch stage, an instruction decode stage, an instruction execute stage, a memory access stage and a result write-back stage. If a co-processor instruction is received by the processor, the co-processor instruction is held in the core processor until the co-processor instruction reaches the memory access stage, at which time the co-processor instruction is transmitted to the co-processor.

Claims

1. A method of processing instructions in a computer system comprising a processor and a co-processor communicatively coupled to the processor, the method comprising:

(a) processing instructions in the processor in an instruction pipeline wherein instructions are processed sequentially by an instruction fetch stage, an instruction decode stage, an instruction execute stage, a memory access stage and a result write-back stage; and

(b) if a co-processor instruction is received by the processor, holding the co-processor instruction in the core processor until the co-processor instruction reaches the memory access stage and then transmitting the co-processor instruction to the co-processor.

2. The method of claim 1 further comprising a step (c) of:

(c) if an interrupt or exception is received by the processor, canceling an instruction that is in the instruction execute stage when the interrupt is received and reissuing the instruction starting at the instruction fetch stage.

3. The method of claim 2 wherein if an interrupt or exception is received by the processor when a co-processor instruction is in the instruction execute stage, the co-processor instruction is canceled before the co-processor instruction is transmitted to the co-processor and the co-processor instruction is reissued starting at the instruction fetch stage.

4. The method of claim 1 wherein step (b) comprises:

if a co-processor instruction is received by the processor, performing steps of;

(b)(i) executing the co-processor instruction during the instruction execute stage, but not transmitting the co-processor instruction to the co-processor during the instruction execute stage; and

(b)(ii) transmitting the co-processor instruction to the co-processor during the memory access stage.

5. The method of claim 4 wherein the processor includes a co-processor interface communicatively coupled to the co-processor, wherein executing step (b)(i) comprises providing the co-processor instruction to the co-processor interface during the instruction execute stage and wherein transmitting step (b)(ii) comprises transmitting the co-processor instruction from the co-processor interface to the co-processor during the memory access stage.

6. The method of claim 1 wherein the co-processor is a processing element for which sending the same co-processor instruction to the co-processor twice decreases the performance of the co-processor.

7. The method of claim 1 wherein the processor is a reduced instruction set computer (RISC) processor.

8. The method of claim 1 wherein the system is a media decoding system, the processor is a core decoder processor and the co-processor is a decoding accelerator adapted to assist the core processor with a decoding function.

9. A computer system comprising:

a processor adapted to process instructions in an instruction pipeline wherein instructions are processed sequentially by an instruction fetch stage, an instruction decode stage, an instruction execute stage, a memory access stage and a result write-back stage; and

a co-processor communicatively coupled to the processor and adapted to perform processing tasks in response to co-processor instructions provided by the processor;

wherein when the processor processes a co-processor instruction, the processor holds the co-processor instruction until the co-processor instruction reaches the memory access stage and then transmits the co-processor instruction to the co-processor.

10. The system of claim 9 wherein if an interrupt is received by the processor, the processor is adapted to cancel an instruction that is in the instruction execute stage when the interrupt is received and to reissue the instruction starting at the instruction fetch stage.

11. The system of claim 10 wherein if an interrupt is received by the processor when a co-processor instruction is in the instruction execute stage, the processor is adapted to cancel the co-processor instruction before the co-processor instruction is transmitted to the co-processor and to reissue the co-processor instruction starting at the instruction fetch stage.

12. The system of claim 9 wherein the processor is adapted to execute a co-processor instruction during the instruction execute stage, but wherein the processor is adapted not to transmit the co-processor instruction to the co-processor until the memory access stage.

13. The system of claim 9 wherein the processor includes a co-processor interface communicatively coupled to the co-processor, wherein the processor is adapted to provide a co-processor instruction to the co-processor interface during the instruction execute stage and wherein the co-processor interface is adapted to transmit the co-processor instruction to the co-processor during the memory access stage.

14. The system of claim 9 wherein the co-processor is a processing element for which sending the same co-processor instruction to the co-processor twice decreases the performance of the co-processor.

15. The system of claim 9 wherein the processor is a reduced instruction set computer (RISC) processor.

16. The system of claim 9 wherein the system is a media decoding system, the processor is a core decoder processor and the co-processor is a decoding accelerator adapted to assist the core processor with a decoding function.