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Risc processor supporting one or more uninterruptible co-processors

  • US 20030188127A1
  • Filed: 04/01/2002
  • Published: 10/02/2003
  • Est. Priority Date: 04/01/2002
  • Status: Active Grant
First Claim
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1. A method of processing instructions in a computer system comprising a processor and a co-processor communicatively coupled to the processor, the method comprising:

  • (a) processing instructions in the processor in an instruction pipeline wherein instructions are processed sequentially by an instruction fetch stage, an instruction decode stage, an instruction execute stage, a memory access stage and a result write-back stage; and

    (b) if a co-processor instruction is received by the processor, holding the co-processor instruction in the core processor until the co-processor instruction reaches the memory access stage and then transmitting the co-processor instruction to the co-processor.

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