Compacting circuit responses

• US 20030188269A1
• Filed: 03/27/2002
• Published: 10/02/2003
• Est. Priority Date: 03/27/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mitra, Subhasish, Kim, Kee Sup
• Granted Patent: US 7,185,253 B2
• Time in Patent Office: Days
• US Class Current: 716/2
• CPC Class Codes: G01R 31/3172 Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test

Abstract

Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrated circuit testing. The number of outputs applied to output pins or other connectors may be substantially decreased, resulting in cost savings.

Claims

1. A method comprising:

providing a compactor characterized by a binary matrix having a row for each of a plurality of circuit elements and a column for each compactor output; and

making all of the matrix rows non-zero and different from each of the other rows.

2. The method of claim 1 including making all of the matrix rows have an odd number of ones.

3. The method of claim 2 including making all of the rows have an equal number of ones.

4. The method of claim 1 including providing a compactor for the outputs of a plurality of circuit elements in the form of scan chains.

5. The method of claim 1 including forming a compactor using exclusive OR gates.

14. The method of claim 1 including forming a compactor using exclusive OR gates.

6. A device comprising:

n input terminals;

m output terminals where m is less than n; and

said device having a binary matrix having a row for each of a plurality of circuit elements and column for each output, all of the matrix rows being non-zero and each of said rows being different from each of the other rows.

7. The device of claim 6 wherein all of the matrix rows have an odd number of ones.

8. The device of claim 7 wherein all of the matrix rows have an equal number of ones.

9. The device of claim 6 wherein said circuit elements are scan chains.

10. The device of claim 9 including an array of exclusive OR gates.

11. A method comprising:

providing a compactor characterized by a binary matrix having a row for each of a plurality of scan chains and a column for each compactor output; and

making all of the matrix rows non-zero and different from each of the other rows.

12. The method of claim 11 including making all of the matrix rows have an odd number of ones.

13. The method of claim 12 including making all of the rows have an equal number of ones.

15. A device to compact scan chain responses comprising:

n input terminals;

m output terminals, where m is less than n; and

said device having a binary matrix having a row for each of a plurality of circuit elements and a column for each output, all of the matrix rows being non-zero and all of said rows being different from each of the other rows.

16. The device of claim 15 wherein all of the matrix rows have an odd number of ones.

17. The device of claim 16 wherein all of the matrix rows have an equal number of ones.

18. The device of claim 15 including an array of exclusive OR gates.

19. The device of claim 15 wherein said device can detect at least two errors in two different scan chains.

20. The device of claim 19 wherein said device can detect at least three errors in three different scan chains.

21. The device of claim 15 wherein said device can detect at least one error and one scan chain and an x-value in another scan chain.

22. A device comprising:

a plurality of inputs;

a plurality of outputs, the number of outputs being less than the number of inputs;

exclusive OR gates coupled between certain of said inputs and certain of said outputs;

at least one exclusive OR gate coupled between each input and at least one output; and

each input being coupled to said outputs differently.

23. The device of claim 22, wherein said inputs are coupled to scan chains in an integrated circuit tester.

24. The device of claim 22, wherein each input is coupled to an odd number of outputs through exclusive OR gates.

25. The device of claim 22, wherein the same number of inputs are coupled to each output.

26. A method comprising:

coupling a plurality of inputs to a smaller number of outputs through exclusive OR gates;

coupling said inputs to said outputs so that at least one exclusive OR gate is coupled between each input and at least one output; and

coupling said inputs to said outputs so that each input is coupled to said outputs differently.

27. The method of claim 26 including coupling said inputs to scan chains in an integrated circuit tester.

28. The method of claim 26 including coupling each input to an odd number of outputs through exclusive OR gates.

29. The method of claim 26 including coupling the same number of inputs to each output.

30. The method of claim 27 including detecting at least two errors in two different scan chains simultaneously.

31. The method of claim 27 including detecting at least three errors simultaneously in three different scan chains.

32. The method of claim 27 including while scanning patterns out in a diagnosis mode, configuring the scan chains into longer scan chains by concatenating multiple scan chains and shifting the contents of these chains out using scan out pins.

33. The method of claim 27 including applying select signals to scan out one or more scan chains directly through scan out pins bypassing a compactor circuit.

34. The method of claim 26 including identifying a failing scan chain and a failing flip flop in a scan chain directly from the compactor outputs collected on a tester without having to configure the scan chains in a diagnosis mode.

35. The method of claim 26 including designing a compactor using the principles that if a single scan chain produces an error at any scan out, the compactor outputs produce an error at that scan cycle if, and only if, no row of the compactor matrix contains all zeros, if two scan chains produce errors at any scan out cycle, the compactor outputs produce an error at that cycle if, and only if, no two rows of a compactor matrix are identical, where three or an odd number of scan chains produce errors at any scan out cycle, the compact outputs produce an error at that scan out cycle if, and only if, the bitwise exclusive-OR of any two rows of a compactor matrix is not equal to any other row of the compactor matrix, if a scan chain produces an error and another scan chain produces a logic value unknown during simulation in any scan out cycle, the compactor outputs produce an error at that scan out cycle if, and only if, no row of the compactor matrix contains all zeros, and if any two rows have one at the same column there must be two columns in which the same rows have (0, 1) and (1, 0) and differentiating the situation where a single scan chain produces an error at the scan out cycle and the compactor outputs produce an error at that scan out cycle if, and only if, the bitwise exclusive-OR of any two rows of the compactor matrix is not equal to any other row of the compactor matrix, and if the bitwise exclusive-OR of two rows of a compactor matrix is equal to a compactor error vector at the scan out cycle, then it is possible that the scan chains corresponding to these two rows produce errors at that scan out cycle.