System and method of preventing the simulation of a circuit if a change to the circuit topology is detected

• US 20030188275A1
• Filed: 03/27/2002
• Published: 10/02/2003
• Est. Priority Date: 03/27/2002
• Status: Abandoned Application

• Current Assignee: Intusoft, Co.
• Original Assignee: Intusoft, Co.
• Inventors: Meares, Lawrence G.
• Application Number:
  US10/112,320
• Publication Number:
  US 20030188275A1
• Time in Patent Office: Days
• US Class Current: 716/4
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A system, method, and software module for preventing a simulation and/or analysis of a circuit described in a netlist if a change in the circuit topology has been detected. The method entails scanning the netlist for circuit topology changes prior to performing the simulation or analysis on the circuit. If no change in the circuit topology has been detected, then the simulation or analysis of the circuit is allowed to proceed. If, on the other hand, a change in the circuit topology has been detected, then in some cases the simulation and/or analysis of the circuit is prevented. The methodology allows a prospective customer to perform simulation and/or analysis on a complicated circuit with a freely-distributed demo simulation program, and yet it does not rise to the software manufacturing giving away its software since the simulation and/or analysis is restricted to that particular circuit topology.

Claims

1. A method, comprising:

receiving a netlist that describes a circuit; and

adding a function to said netlist to prevent a simulation and/or analysis of said circuit if a change in the topology of said circuit is detected.

2. The method of claim 1, wherein adding said function comprises:

generating.a reference value which is dependent on said topology of said circuit; and

adding said function to said netlist with said reference value as an argument to said function.

3. The method of claim 2, wherein generating said reference value comprises performing a hash operation on at least a portion of circuit topology parameters of said netlist.

4. The method of claim 2, wherein generating said reference value comprises:

selecting one or more circuit topology parameters from each line of said netlist; and

using said selected one or more circuit topology parameters of each line of said netlist as inputs to a mathematical algorithm to generate said reference value.

5. The method of claim 4, wherein selecting one or more circuit topology parameters from each line of said netlist is performed in a pseudo random fashion.

6. A method, comprising:

receiving a netlist that describes a circuit;

determining whether said topology of said circuit has changed;

performing a circuit simulation and/or analysis of said circuit in response to determining that said topology of said circuit has not changed; and

denying a circuit simulation and/or analysis of said circuit in response to determining that said topology of said circuit has changed.

7. The method of claim 6, wherein said netlist comprises a function used to detect whether said topology of said circuit has been changed.

8. The method of claim 7, wherein said function includes a first argument used to select circuit topology parameters from each line of said netlist and a second argument that serves as a reference value indicative of an original circuit topology for said netlist.

9. The method of claim 8, wherein determining whether said topology of said circuit has changed comprises:

using said first argument to select one or more circuit topology parameters from each line of said netlist;

performing a mathematical operation on said selected one or more circuit topology parameters from each line of said netlist to generate a test value; and

comparing said test value with said reference value to determine whether said circuit topology has changed.

10. The method of claim 9, wherein said first argument is used as an input to a pseudo random number generator which generates a number used to select the number of circuit topology parameters for each of said line of said netlist.

11. The method of claim 9, wherein said mathematical operation comprises a hashing operation.

12. The method of claim 6, further comprising:

determining whether the number of components and/or nodes in said netlist is below and/or above a predetermined limit;

performing said circuit simulation and/or analysis of said circuit in response to determining that the number of components and/or nodes in said netlist is below said predetermined limit; and

denying said circuit simulation and/or analysis of said circuit in response to determining that the number of components and/or nodes in said netlist is above said predetermined limit.

13. A computer readable medium storing one or more software modules to add a function to said netlist that prevents a simulation and/or analysis of said circuit if a change in the topology of said circuit is detected.

14. The computer readable medium of claim 13, wherein said one or more software modules:

generates a reference value dependent on said topology of said circuit; and

adds said function to said netlist with said reference value as an argument to said function.

15. The computer readable medium of claim 14, wherein said one or more software modules generates said reference value by performing a hash operation on at least a portion of circuit topology parameters of said netlist.

16. The computer readable medium of claim 14, wherein said one or more software modules generates said reference value by:

selecting one or more circuit topology parameters from each line of said netlist; and

using said one or more circuit topology of each line of said netlist as inputs to a mathematical algorithm to generate said reference value.

17. The computer readable medium of claim 16, wherein said one or more software modules selects one or more circuit topology parameters from each line of said netlist in a pseudo random fashion.

18. A computer readable medium storing one or more software modules to:

determine whether a topology of a circuit described in a netlist has changed;

perform a circuit simulation and/or analysis of said circuit in response to determining that said topology of said circuit has not changed; and

denying a circuit simulation and/or analysis of said circuit in response to determining that said topology of said circuit has changed.

19. The computer readable medium of claim 18, wherein said one or more software modules executes a function in said netlist to cause said determination of whether said topology of said circuit has been changed.

20. The computer readable medium of claim 19, wherein said function includes a first argument that serves to select circuit topology parameters from each line of said netlist and a second argument that serves as a reference value indicative of an original circuit topology for said netlist.

21. The computer readable medium of claim 20, wherein said one or more software modules determines whether said topology of said circuit has changed by:

using said first argument to select one or more circuit topology parameters from each line of said netlist;

performing a mathematical operation on said selected one or more circuit topology parameters from each line of said netlist to generate a test value; and

comparing said test value with said reference value to determine whether said circuit topology has changed.

22. The computer readable medium of claim 21, wherein said one or more software modules uses said first argument as an input to a pseudo random number generator to generate a number used to select the number of circuit topology parameters for each of said line of said netlist.

23. The computer readable medium of claim 21, wherein said mathematical operation comprises a hashing operation.

24. The computer readable medium of claim 18, wherein said one or more software modules:

determines whether the number of components and/or nodes in said netlist is below and/or above a predetermined limit;

performs said circuit simulation and/or analysis of said circuit in response to determining that the number of components and/or nodes in said netlist is below said predetermined limit; and

denying said circuit simulation and/or analysis of said circuit in response to determining that the number of components and/or nodes in said netlist is above said predetermined limit.

25. An apparatus including a processor to add a function to a netlist that prevents a simulation and/or analysis of said circuit if a change in the topology of said circuit is detected.

26. The apparatus of claim 25, wherein said processor:

generates a reference value that is dependent on said topology of said circuit; and

adds said function to said netlist with said reference value as an argument to said function.

27. The apparatus of claim 26, wherein said processor generates said reference value by performing a hash operation on at least a portion of circuit topology parameters of said netlist.

28. The apparatus of claim 26, wherein said processor generates said reference value by:

selecting one or more circuit topology parameters from each line of said netlist; and

using said selected one or more circuit topology of each line of said netlist as inputs to a mathematical algorithm to generate said reference value.

29. The apparatus of claim 28, wherein said processor selects one or more circuit topology parameters from each line of said netlist in a pseudo random fashion.

30. An apparatus comprising a processor to:

determine whether a topology of a circuit described in a netlist has changed;

perform a circuit simulation and/or analysis of said circuit in response to determining that said topology of said circuit has not changed; and

denying a circuit simulation and/or analysis of said circuit in response to determining that said topology of said circuit has changed.

31. The apparatus of claim 30, wherein said processor executes a function in said netlist to cause said determination of whether said topology of said circuit has been changed.

32. The apparatus of claim 31, wherein said function includes a first argument that serves to select circuit topology parameters from each line of said netlist and a second argument that serves as a reference value indicative of an original circuit topology for said netlist.

33. The apparatus of claim 32, wherein said processor determines whether said topology of said circuit has changed by:

using said first argument to select one or more circuit topology parameters from each line of said netlist;

performing a mathematical operation on said selected one or more circuit topology parameters from each line of said netlist to generate a test value; and

comparing said test value with said reference value to determine whether said circuit topology has changed.

34. The apparatus of claim 33, wherein said processor generates a pseudo random number in response to said first argument, said pseudo random number being used to select the number of circuit topology parameters from each of said line of said netlist.

35. The apparatus of claim 33, wherein said mathematical operation comprises a hashing operation.

36. The apparatus of claim 30, wherein said processor:

determines whether the number of components and/or nodes in said netlist is below and/or above a predetermined limit;

performs said circuit simulation and/or analysis of said circuit in response to determining that the number of components and/or nodes in said netlist is below said predetermined limit; and

denying said circuit simulation and/or analysis of said circuit in response to determining that the number of components and/or nodes in said netlist is above said predetermined limit.