Nanowire devices and methods of fabrication

• US 20030189202A1
• Filed: 04/05/2002
• Published: 10/09/2003
• Est. Priority Date: 04/05/2002
• Status: Abandoned Application

• Current Assignee: Integrated Nanosystems Incorporated
• Original Assignee: Integrated Nanosystems Incorporated
• Inventors: Cassell, Alan M., Li, Jun, Han, Jie
• Application Number:
  US10/117,965
• Publication Number:
  US 20030189202A1
• Time in Patent Office: Days
• US Class Current: 257/14
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: C04B 2235/3284 Zinc oxides, zincates, cadmium oxides, cadmiates, mercury oxides, mercurates or oxide forming salts thereof
• CPC Class Codes: C04B 2235/3287 Germanium oxides, germanates or oxide forming salts thereof, e.g. copper germanate
• CPC Class Codes: C04B 2235/447 Phosphates or phosphites, e.g. orthophosphate or hypophosphite
• CPC Class Codes: C04B 2235/526 characterised by the length of the fibers
• CPC Class Codes: C04B 2235/5264 characterised by the diameter of the fibers
• CPC Class Codes: C04B 2235/5288 Carbon nanotubes
• CPC Class Codes: C04B 35/62807 Silica or silicates
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 29/605 Products containing multiple oriented crystallites, e.g. columnar crystallites
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02491 Conductive materials
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/02653 Vapour-liquid-solid growth
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2221/1094 Conducting structures comprising nanotubes or nanowires
• CPC Class Codes: H01L 23/53276 containing carbon, e.g. fullerenes superconducting fullerenes H10N60/853
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/20 : including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/66469 : with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10K 10/00 : Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers integrated devices or assemblies of multiple devices H10K19/00
• CPC Class Codes: H10K 10/82 : Electrodes
• CPC Class Codes: H10K 85/221 : Carbon nanotubes

Abstract

Nanowire devices are provided based on carbon nanotubes or single-crystal semiconductor nanowires. The nanowire devices may be formed on a silicon substrate or other suitable substrate. Electrodes may be patterned on the substrate. Catalyst sites may be formed on the electrodes prior to nanowire growth. Chemical vapor deposition techniques may be used to grow the nanowires at the catalyst sites. A material such as an insulator may be formed on the nanowires following nanowire growth. The insulator may be planarized using chemical-mechanical polishing or other suitable techniques. The resulting nanowire device may be used in chemical or biological sensors, as a field emitter for displays, or for other applications.

Claims

1. A nanowire device comprising:

a substrate;

a plurality of corresponding patterned electrodes on the substrate;

a plurality of catalyst sites on each of the patterned electrodes;

a plurality of corresponding nanowires grown from the catalyst sites; and

a dielectric material deposited on the nanowires such that the dielectric material fills at least some volume between adjacent nanowires, enhances the strength of the nanowires, and provides electrical insulation between the nanowires, wherein the dielectric material is planarized to form a planarized surface at which tips of the nanowires are located.

2. The nanowire device defined in claim 1 wherein the nanowires comprise carbon nanotubes.

3. The nanowire device defined in claim 1 wherein the nanowires comprise single-crystal semiconductor nanowires.

4. The nanowire device defined in claim 1 wherein the dielectric material is silicon oxide.

5. The nanowire device defined in claim 1 wherein the substrate is silicon, wherein the dielectric material is chemically-mechanically polished silicon oxide, and wherein the nanowires are carbon nanotubes.

6. The nanowire device defined in claim 1 wherein the electrode pads have lateral dimensions in the range of 0.2-20 μ

m.

7. The nanowire device defined in claim 1 wherein there are at least nine electrodes in the device.

8. The nanowire device defined in claim 1 wherein at least some of the nanowires have diameters in the range of 10 nm to 100 nm.

9. The nanowire device defined in claim 1 wherein the substrate is silicon, the dielectric material includes silicon oxide, the nanowires comprise carbon nanotubes at least some of which have diameters in the range of 10 nm to 100 nm and lengths of more than 0.5 μ

m.

10. The nanowire device defined in claim 1 wherein the catalyst sites are arranged on the electrodes in a regular pattern.

11. A method for fabricating a nanowire device, comprising:

forming at least one metal electrode on a substrate;

depositing resist on the electrode;

patterning the resist using e-beam lithography to establish at least one hole that defines at least one catalyst site where catalyst is to be deposited;

depositing a layer of catalyst metal on top of the patterned resist and in the hole;

removing the patterned resist after depositing the layer of catalyst metal so that catalyst remains in the catalyst site defined by the hole; and

growing a nanowire from the catalyst site.

12. The method defined in claim 11 wherein the resist is patterned to establish a plurality of holes that define a plurality of catalyst sites from which a plurality of corresponding nanowires are grown, the method further comprising depositing an insulator on top of the nanowires.

13. The method defined in claim 11 wherein the resist is patterned to establish a plurality of holes that define a plurality of catalyst sites from which a plurality of corresponding nanowires are grown, the method further comprising depositing a layer of insulating material on top of the nanowires and planarizing the deposited material so that tips of the nanowires are exposed.

14. The method defined in claim 11 wherein the resist is patterned to establish a plurality of holes that define a plurality of catalyst sites from which a plurality of corresponding nanowires are grown, the method further comprising depositing a layer of insulator on top of the nanowires and planarizing the deposited insulator so that tips of the nanowires are exposed.

15. The method defined in claim 11 wherein the resist is patterned to establish a plurality of holes that define a plurality of catalyst sites from which a plurality of nanowires are grown, the method further comprising depositing a layer of silicon dioxide on top of the nanowires and planarizing the deposited oxide so that tips of the nanowires are exposed.

16. The method defined in claim 11 wherein forming at least one metal electrode on the substrate comprises forming a plurality of electrodes on the substrate.

17. The method defined in claim 11 wherein the substrate comprises a silicon wafer, wherein forming at least one metal electrode on the substrate comprises forming a plurality of electrodes on the substrate, wherein the resist is patterned to establish a plurality of holes on each electrode that define a plurality of catalyst sites from which a plurality of nanowires are grown, the method further comprising depositing a layer of insulator on top of the nanowires and planarizing the deposited insulator so that tips of the nanowires are exposed.

18. A method for forming a nanowire device comprising:

forming a plurality of metal electrodes on a substrate;

forming a plurality of catalyst sites on each electrode;

growing nanowires from the catalyst sites;

depositing a layer of dielectric on top of the nanowires; and

planarizing the dielectric after deposition so that tips of the nanowires are exposed.

19. The method defined in claim 18 wherein the metal electrodes include a metal selected from the group consisting of titanium, gold, and platinum, wherein the catalyst sites include a metal selected from the group consisting of nickel and gold, and wherein the substrate includes a material selected from the group consisting of silicon, quartz, sapphire, and glass.

20. The method defined in claim 18 wherein the nanowires comprise doped semiconductors.