Precision zener diodes and methods of manufacturing precision zener diodes

• US 20030189220A1
• Filed: 04/08/2002
• Published: 10/09/2003
• Est. Priority Date: 04/08/2002
• Status: Active Grant

• Current Assignee: Fab-Tech, Inc. (Exyte AG)
• Original Assignee: Fab-Tech, Inc. (Exyte AG)
• Inventors: Hamerski, Roman J.
• Granted Patent: US 6,791,161 B2
• Time in Patent Office: Days
• US Class Current: 257/200
• CPC Class Codes: H01L 29/66106 Zener diodes
• CPC Class Codes: H01L 29/866 Zener diodes

Abstract

Precision Zener diodes, methods for manufacturing precision Zener diodes, and consumer electronics employing the Zener diodes are disclosed. The Zener diodes are made from a semiconductor substrate layer on which is grown an epitaxial layer. The epitaxial layer has a resistivity greater than that of the substrate. The diode also has an interior region of doped semiconductor material of the same conductivity type as the substrate. The interior region extends through the epitaxial layer and into the substrate layer. The diode also has a junction layer of a conductivity type different from the substrate. The junction layer is formed in the epitaxial surface, and the junction layer forms an interior P/N junction with the interior region and a peripheral P/N junction with a peripheral portion of the device.

Claims

1. A semiconductor device having a first electrode and a second electrode, the device comprising:

a semiconductor substrate layer of a substrate conductivity type and of a substrate resistivity;

an epitaxial layer grown on the substrate layer, the epitaxial layer having an epitaxial layer conductivity type consistent with the substrate conductivity type, the epitaxial layer having an epitaxial layer resistivity greater than the substrate resistivity, the epitaxial layer having an epitaxial surface opposite to the substrate layer;

an interior region of doped semiconductor material having an interior conductivity type consistent with the substrate conductivity type, the interior region extending into the epitaxial layer; and

a junction layer of a junction conductivity type different from the substrate conductivity type formed in the epitaxial surface, the junction layer forming an interior P/N junction with the interior region and the junction layer forming a peripheral P/N junction with a peripheral portion of the device.

2. The device as set forth in claim 1, wherein the first electrode is an anode and the second electrode is a cathode.

3. The device as set forth in claim 1, wherein the substrate conductivity type is N-type.

4. The device as set forth in claim 3, wherein the substrate layer is doped with arsenic.

5. The device as set forth in claim 3, wherein the substrate layer is doped with antimony.

6. The device as set forth in claim 1, wherein the epitaxial layer is of a thickness ranging from about 6 microns to about 15 microns.

7. The device as set forth in claim 1, wherein the substrate resistivity is in the range of about 1E-3 ohm-cm to about 5E-3 ohm-cm.

8. The device as set forth in claim 1, wherein the interior region is produced by ion implantation of phosphorous.

9. The device as set forth in claim 1, wherein the junction layer is produced by ion implantation of boron.

10. The device as set forth in claim 1 further comprising a low contact resistance layer implanted into an exterior surface of the junction layer.

11. The device as set forth in claim 1, wherein the interior P/N junction has an interior breakdown voltage lower than an peripheral breakdown voltage associated with the peripheral P/N junction.

12. A Zener diode having an anode and a cathode, the diode packaged within an insulating package, the diode having conductive leads electrically coupled to the anode and to the cathode respectively, the diode comprising:

a semiconductor base layer of a base layer conductivity type and of a base layer resistivity;

a surface layer grown on the base layer, the surface layer having a surface layer conductivity type the same as the base layer conductivity type, the surface layer having a surface layer resistivity greater than the base layer resistivity, the surface layer in contact with the base layer and having an exterior surface opposite to the base layer;

an internal region of semiconductor material having an internal region conductivity type consistent with the base layer conductivity type, the internal region extending through the surface layer and into the base layer; and

a contact layer of a contact conductivity type opposite to the base layer conductivity type implanted at the exterior surface, the contact layer completing a central semiconductor junction with the internal region and the contact layer completing an edge semiconductor junction with edge portions of the base layer.

13. The diode as set forth in claim 12, wherein the base layer is an epitaxial layer.

14. A consumer electronic product comprising:

a housing operable to enclose and to protect electronics internal to the product;

a user interface; and

electrical circuitry operable to provide electrical signals to the user interface, the electrical circuitry including a Zener diode comprising;

a semiconductor substrate layer of a substrate conductivity type and of a substrate resistivity;

an epitaxial layer grown on the substrate layer, the epitaxial layer having an epitaxial layer conductivity type consistent with the substrate conductivity type, the epitaxial layer having an epitaxial layer resistivity greater than the substrate resistivity, the epitaxial layer having an epitaxial surface opposing the substrate layer;

an interior region of doped semiconductor material having an interior conductivity type consistent with the substrate conductivity type, the interior region extending through the epitaxial layer and into the substrate layer; and

a junction layer of a junction conductivity type different from the substrate conductivity type formed in the epitaxial surface, the junction layer forming an interior P/N junction with the interior region and the junction layer forming a peripheral P/N junction with a peripheral portion of the device.

15. The product as recited in claim 14, wherein the user interface is operable to provide interface functions of at least one of a television, a wireless communication device, a mobile computer system, and a fixed computer system.

16. A method of manufacturing a semiconductor device, the method comprising:

depositing an epitaxial layer on a semiconductor substrate, the substrate doped with material of a substrate dopant type, the substrate having a substrate resistivity;

implanting interior dopant ions of an interior region dopant type consistent with the substrate dopant type, the interior dopant ions entering the crystal structure of the epitaxial layer and the substrate forming an interior region extending through the epitaxial layer and into the substrate; and

implanting junction dopant ions of a junction dopant type different from the substrate dopant type the junction dopant ions entering a crystal structure of the epitaxial layer and forming a junction layer, the junction layer forming an interior P/N junction with the interior region and the junction layer forming a peripheral P/N junction with a peripheral portion of the device.

17. The method as set forth in claim 16, wherein the interior dopant ions are implanted at an energy of greater than 40 KeV.

18. The method as set forth in claim 16, wherein the interior dopant ions are acceptor dopant ions.

19. The method as set forth in claim 18, wherein the acceptor dopant ions are comprised of phosphorous.

20. The method as set forth in claim 16, wherein the junction dopant ions are donor dopant ions.

21. The method as set forth in claim 20, wherein the donor dopant ions are comprised of boron.

22. The method as set forth in claim 16 further comprising implanting a low contact resistance layer into an exterior surface of the junction layer at a lower energy than used in connection with forming the junction layer.

23. The method as set forth in claim 16 further comprising at least one longer duration high temperature heating process to diffuse and activate the interior dopant ions.

24. The method as set forth in claim 16 further comprising at least one shorter duration high temperature heating process to activate the junction dopant ions.