Semiconductor device and method for manufacturing the same

• US 20030189259A1
• Filed: 04/03/2003
• Published: 10/09/2003
• Est. Priority Date: 04/05/2002
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Kurita, Yoichiro, Shironouchi, Toshiaki, Tetsuka, Takashi
• Granted Patent: US 6,930,396 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/2612 Auxiliary members for layer connectors, e.g. spacers
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 24/27 Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/743 : Apparatus for manufacturing layer connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

There is provided a semiconductor device in which a plurality of semiconductor chips is stacked in layers and sealed in a package, including: a lower-layer semiconductor chip which is mounted on a package board; an upper-layer semiconductor chip which is stacked via a plurality of spacers on the lower-layer semiconductor chip; at least one first conductor interconnecting electrically at least one first electrode on the lower-layer semiconductor chip and at least one first internal terminal on the package board; at least one second conductor electrically interconnecting at least one second electrode on the upper-layer semiconductor chip and at least one second internal terminal on the package board; and the package for sealing therein the lower-layer semiconductor chip, the upper-layer semiconductor chip, and the at least one first conductor and the at least one second conductor which are all on the package board.

Claims

1. A semiconductor device in which a plurality of semiconductor chips is stacked in layers and sealed in a package, wherein:

an upper-layer semiconductor chip is stacked via a plurality of spacers on a lower-layer semiconductor chip;

at least one of said plurality of spacers is formed on said lower-layer semiconductor chip; and

said upper-layer semiconductor chip, said plurality of spacers, and said lower-layer semiconductor chip are sealed in said package.

2. The semiconductor device according to claim 1, wherein said plurality of spacers is made up of a projecting structure.

3. The semiconductor device according to claim 1, wherein said package is made up of an insulator.

4. The semiconductor device according to claim 1, wherein said package is made up of a container which seals therein an inert gas.

5. The semiconductor device according to claim 1, wherein said plurality of spacers is made up of an insulator.

6. The semiconductor device according to claim 5, wherein said insulator is made of thermo-hardening resin, fast-hardening resin, or photo-hardening resin.

7. The semiconductor device according to claim 1, wherein said upper-layer semiconductor chip is stacked via an adhesive agent on said lower-layer semiconductor chip.

8. The semiconductor device according to claim 7, wherein said adhesive agent is made of thermo-hardening resin.

9. The semiconductor device according to claim 1, wherein said plurality of spacers is made up of a conductor.

10. The semiconductor device according to claim 1, wherein an insulating sheet is formed on a surface of said upper-layer semiconductor chip, said surface facing said lower-layer semiconductor chip.

11. The semiconductor device according to claim 1, wherein said plurality of semiconductor chips stacked in said layers is different in size from each other.

12. The semiconductor device according to claim 1, wherein connection in a flip-chip manner is applied to at least one semiconductor chip out of said plurality of semiconductor chips stacked in said layers.

13. A semiconductor device in which a plurality of semiconductor chips is stacked in layers and sealed in a package, comprising:

a lower-layer semiconductor chip which is mounted on a package board;

an upper-layer semiconductor chip which is stacked via a plurality of spacers on said lower-layer semiconductor chip;

at least one first conductor interconnecting electrically at least one first electrode on said lower-layer semiconductor chip and at least one first internal terminal on said package board;

at least one second conductor electrically interconnecting at least one second electrode on said upper-layer semiconductor chip and at least one second internal terminal on said package board; and

said package sealing therein said lower-layer semiconductor chip, said upper-layer semiconductor chip, and said at least one first conductor and said at least one second conductor which are all on said package board.

14. The semiconductor device according to claim 13, wherein said plurality of spacers is made up of a projecting structure.

15. The semiconductor device according to claim 13, wherein said package is made up of an insulator.

16. The semiconductor device according to claim 13, wherein said package is made up of a container which seals therein an inert gas.

17. The semiconductor device according to claim 13, wherein said plurality of spacers is made up of an insulator.

18. The semiconductor device according to claim 17, wherein said insulator is made of thermo-hardening resin, fast-hardening resin, or photo-hardening resin.

19. The semiconductor device according to claim 13, wherein said upper-layer semiconductor chip is stacked via an adhesive agent on said lower-layer semiconductor chip.

20. The semiconductor device according to claim 19, wherein said adhesive agent is made of thermo-hardening resin.

21. The semiconductor device according to claim 13, wherein said plurality of spacers is made up of a conductor.

22. The semiconductor device according to claim 13, wherein an insulating sheet is formed on a surface of said upper-layer semiconductor chip, said surface facing said lower-layer semiconductor chip.

23. The semiconductor device according to claim 13, wherein said package board is made of an insulating board.

24. The semiconductor device according to claim 23, wherein at least one external terminal is formed on a back side which is opposite to a right side of said package board on which said at least one first internal terminal and said at least one second terminal are respectively formed.

25. The semiconductor device according to claim 13, wherein said plurality of semiconductor chips stacked in said layers is different in size from each other.

26. The semiconductor device according to claim 13, wherein connection in a flip-chip manner is applied to at least one semiconductor chip out of said plurality of semiconductor chips stacked in said layers.

27. The semiconductor device according to claim 13, wherein connection in a flip-chip manner is applied to at least one of said plurality of semiconductor chips is, in stead of using said at least one first conductor or said at least one second conductor.

28. A semiconductor device manufacturing method for stacking a plurality of semiconductor chips in layers and sealing said plurality of semiconductor chips in a package, comprising the steps of:

forming a plurality of spacers on a lower-layer semiconductor chip;

stacking an upper-layer semiconductor chip via said plurality of spacers on said lower-layer semiconductor chip; and

sealing said lower-layer semiconductor chips, said plurality of spacers, and said upper-layer semiconductor chip in an insulating material making up said package.

29. A semiconductor device manufacturing method for stacking a plurality of semiconductor chips in layers and sealing said plurality of semiconductor chips in a package, comprising:

a lower-layer semiconductor chip mounting step of mounting a lower-layer semiconductor chip on a package board;

a first connecting step of interconnecting electrically at least one first internal terminal on said package board and at least one first electrode on said lower-layer semiconductor chip using at least one first conductor;

a spacer formation step of forming a plurality of spacers on said lower-layer semiconductor chip;

an upper-layer semiconductor chip stacking step of stacking an upper-layer semiconductor chip via said plurality of spacers on said lower-layer semiconductor chip;

a second connecting step of interconnecting electrically at least one second internal terminal on said package board and at least one second electrode on said upper-layer semiconductor chip using at least one second conductor; and

a sealing step of sealing said lower-layer semiconductor chip, said upper-layer semiconductor chip, and said at least one first conductor and said at least one second conductor in an insulating material making up said package.

30. The semiconductor device manufacturing method according to claim 29, wherein said spacer formation step is performed after said first connecting step.

31. The semiconductor device manufacturing method according to claim 29, wherein said spacer formation step is performed before said first connecting step.

32. The semiconductor device manufacturing method according to claim 29 wherein said spacer formation step is performed by supplying liquid resin and then hardening said liquid resin.

33. The semiconductor device manufacturing method according to claim 32, wherein said liquid resin is supplied using a potting method, a screen printing method, or a non-contact type jet dispenser method.

34. The semiconductor device manufacturing method according to claim 29, wherein said method comprises an adhesive agent formation step of forming an adhesive agent on said lower-layer semiconductor chip before said upper-layer semiconductor chip stacking step.

35. The semiconductor device manufacturing method according to claim 29, wherein said method comprises an insulating sheet formation step of forming an insulating sheet on a surface of said upper-layer semiconductor chip, said surface facing said lower-layer semiconductor chip, before said upper-layer semiconductor chip stacking step.

36. The semiconductor device manufacturing method according to claim 29, wherein said spacer formation step is performed using thermo-hardening resin, fast-hardening resin, or photo-hardening resin.

37. The semiconductor device manufacturing method according to claim 29, wherein said spacer formation step is performed by supplying an adhesive agent into which a particulate insulating material is mixed.

38. The semiconductor device manufacturing method according to claim 29, wherein, in said first connecting step, at least one first internal terminal on said package board and at least one first electrode on said lower-layer semiconductor chip are interconnected electrically using a first flip-chip connection method, in stead of said first conductor.

39. The semiconductor device manufacturing method according to claim 29, wherein, in said second connecting step, at least one second internal terminal on said package board and at least one second electrode on said lower-layer semiconductor chip are interconnected electrically using a second flip-chip connection method, in stead of said second conductor.