Multi-level flash memory with temperature compensation

• US 20030189856A1
• Filed: 11/19/2002
• Published: 10/09/2003
• Est. Priority Date: 04/04/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Tae-Hee, Lee, Yeong-Taek
• Granted Patent: US 6,870,766 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A multi-level semiconductor memory device preferably includes a plurality of wordlines connected to memory cells configured to store multi-level data. A first circuit supplies a temperature-responsive voltage to a selected wordline in order to read a state of a selected memory cell. A second circuit supplies a predetermined voltage to non-selected wordlines. The first circuit preferably includes a semiconductor element that varies its resistance in accordance with temperature. Reliable program-verifying and reading functions are preferably provided despite migration of threshold voltage distribution profiles due to temperature variations.

Claims

1. A semiconductor memory device comprising:

a plurality of memory cells configured to store multi-level data;

a plurality of wordlines connected to the plurality of memory cells; and

a first circuit configured to supply a temperature-dependent voltage to a selected one of the wordlines to read or verify a state of a selected memory cell.

2. The semiconductor memory device according to claim 1, further comprising a second circuit configured to supply predetermined voltages to non-selected wordlines to read or verify a state of the selected memory cell.

3. The semiconductor memory device according to claim 1, wherein the first circuit comprises a variable resistance semiconductor element configured to respond to temperature variations.

4. The semiconductor memory device according to claim 1, wherein the first circuit comprises a first voltage generation circuit configured to supply a reference voltage and a second voltage generation circuit configured to supply a flexible reference voltage.

5. The semiconductor memory device according to claim 4, wherein the first circuit further comprises a differential amplifier configured to compare the reference voltage with the flexible reference voltage.

6. The semiconductor memory device according to claim 5, wherein an output of the differential amplifier supplies the temperature-dependent voltage to the selected one of the wordlines.

7. The semiconductor memory device according to claim 4, wherein a voltage level of the temperature-dependent voltage is approximately equal to a voltage level of the flexible reference voltage minus a voltage level of the reference voltage.

8. The semiconductor memory device according to claim 4, wherein the flexible reference voltage is configured to vary based on temperature variations.

9. The semiconductor memory device according to claim 8, wherein the second voltage generation circuit comprises a variable resistance semiconductor element configured to respond to temperature variations.

10. A semiconductor memory device comprising:

a memory cell array comprising a plurality of memory cells, wordlines, and bitlines, said memory cells configured to store multi-level data;

a first voltage generation circuit configured to generate a first voltage having a predetermined level;

a second voltage generation circuit configured to generate a temperature-dependent flexible reference voltage; and

a third circuit configured to compare the first voltage to the flexible reference voltage, said third circuit further configured to supply a temperature-dependent output voltage to a selected one of the wordlines, said output voltage corresponding to a difference between the first voltage and the flexible reference voltage.

11. The semiconductor memory device according to claim 10, further comprising a fourth circuit configured to supply voltages having predetermined levels to nonselected wordlines.

12. The semiconductor memory device of claim 10, wherein the second voltage generation circuit comprises a variable-resistance semiconductor element that responds to temperature variations.

13. The semiconductor memory device of claim 10, wherein the third circuit comprises a differential amplifier configured to receive an input corresponding to the first voltage into a first input terminal thereof, to receive an input corresponding to the flexible reference voltage into a second input terminal thereof, and to output the output voltage from an output terminal thereof.

14. The semiconductor memory device of claim 13, wherein the third circuit further comprises a first resistance element coupled between the first input terminal and the first voltage generation circuit and a second resistance element coupled between the second input terminal and the second voltage generation circuit.

15. A method of operating a multi-level data state semiconductor memory device having a plurality of wordlines connected to a plurality of memory cells, said method comprising:

selecting a wordline from among a plurality of wordlines, said selected wordline corresponding to a selected memory cell;

supplying a temperature-dependent voltage to the selected wordline; and

supplying predetermined voltages to nonselected wordlines.

16. The method according to claim 15, further comprising reading a data state of the selected memory cell.

17. The method according to claim 15, further comprising verifying a program state of the selected memory cell.

18. The method according to claim 15, further comprising generating a fixed reference voltage and a temperature-dependent flexible reference voltage.

19. The method according to claim 18, further comprising comparing the fixed reference voltage with the flexible reference voltage to generate the temperature-dependent voltage to supply to the selected wordline.

20. The method according to claim 15, wherein supplying predetermined voltages to nonselected wordlines comprises supplying a pass voltage to nonselected wordlines.