Multi-layer printed circuit board fabrication system and method
First Claim
Patent Images
1. A method for aligning an image to be recorded by a direct image scanner on an upper layer of a printed circuit board with an image recorded on a lower layer thereof, the method comprising:
- visually imaging a portion of the image on the lower layer; and
recording a pattern on the upper layer, referenced to coordinates of the visual image of the portion.
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Accused Products
Abstract
A method for aligning an image to be recorded by a direct image scanner on an upper layer of a printed circuit board with an image recorded on a lower layer thereof, the method comprising:
visually imaging a portion of the image on the lower layer; and
recording a pattern on the upper layer, referenced to coordinates of the visual image of the portion.
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Citations
55 Claims
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1. A method for aligning an image to be recorded by a direct image scanner on an upper layer of a printed circuit board with an image recorded on a lower layer thereof, the method comprising:
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visually imaging a portion of the image on the lower layer; and
recording a pattern on the upper layer, referenced to coordinates of the visual image of the portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method for aligning an image to be recorded by a direct image scanner on an upper layer of a printed circuit board substrate with a pattern on a lower layer thereof, the method comprising:
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detecting at least one hole provided in the upper layer, said at least one hole being provided in predetermined alignment to said pattern and said at least one hole not passing through said lower layer; and
scanning a pattern on the upper layer in predetermined alignment with said at least one hole.
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17. A method for recording an image on an upper layer of a multi-layered printed circuit board substrate, the method comprising:
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forming at least one hole in an upper layer of a multi-layered printed circuit board substrate, said at least one hole having a known spatial orientation to a pattern formed on one layer of the substrate and said substrate having at least two layers of circuitry already formed thereon;
acquiring an image of the at least one hole;
calculating a location of the at least one hole from analysis of the image; and
recording a pattern on the upper layer with reference to said location. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A method of image alignment, comprising:
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producing an array of elements arranged in a non-periodic pattern on said image; and
matching said pattern with an identical pattern, such that said image is aligned when the patterns overlay each other, wherein fewer than 50% of the elements of the alignment pattern in the image overlay the pattern in the identical pattern for any position in which the patterns are not aligned.
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28. Apparatus for recording an electrical circuit pattern on an upper layer of a multi-layer printed circuit board substrate, comprising:
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an alignment pattern generator generating an alignment pattern that is visible on the upper surface of the multi-layer printed circuit board substrate, said alignment pattern having a known orientation with respect to an electrical circuit pattern formed on one non-upper layer of the substrate, said substrate having at least two layers of circuitry already formed thereon;
an alignment pattern location sensor sensing a location of the alignment pattern; and
an electrical circuit pattern generator recording an electrical circuit pattern on said upper surface in a desired orientation with reference to the alignment pattern. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
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42. Apparatus for aligning a first electrical circuit pattern to be recorded on an upper layer of a multi-layer printed circuit board substrate to a second electrical circuit pattern formed on a lower layer of the multi-layer printed circuit board substrate, comprising:
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an alignment pattern location sensor sensing a location of an alignment pattern located on a multi-layered printed circuit board substrate, said alignment pattern having a known orientation to said second electrical circuit pattern; and
an electrical circuit pattern generator recording an electrical circuit pattern on said upper surface in a desired orientation with reference to the alignment pattern. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55)
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Specification