Integrated circuit incorporating RF antenna switch and power amplifier

• US 20030190895A1
• Filed: 04/02/2002
• Published: 10/09/2003
• Est. Priority Date: 04/02/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Leipold, Dirk, Mostov, Alexander
• Granted Patent: US 6,882,829 B2
• Time in Patent Office: Days
• US Class Current: 455/78
• CPC Class Codes: H04B 1/04 Circuits
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

A novel integrated circuit incorporating a transmit/receive antenna switch capable of being integrated using silicon based RF CMOS semiconductor processes and a power amplifier on the same substrate. The switch circuit is constructed whereby the substrate (i.e. bulk) terminals of the FETs are left floating thus improving the isolation and reducing the insertion loss of the switch. Floating the substrate of the transistors eliminates most of the losses caused by leakage paths through parasitic capacitances internal to the transistor thus improving the isolation and reducing the insertion loss of the switch. Alternatively, the substrate can be connected to the source or to ground via a resistor of sufficiently high value to effectively float the substrate.

Claims

1. A Radio Frequency (RF) antenna switch circuit, comprising:

first coupling means for electrically coupling an antenna to a transmitter circuit;

second coupling means for electrically coupling said antenna to a receiver circuit;

control means for establishing a signal path from said antenna to either said transmit circuit or said receiver circuit in accordance with a transmit/receive control signal; and

wherein said first coupling means and said second coupling means each comprise one or more field effect transistors (FETs) whose substrate terminals are configured to be substantially electrically floating.

2. The circuit according to claim 1, wherein said signal path comprises a substantially low impedance signal path.

3. The circuit according to claim 1, wherein said first coupling means comprises a single field effect transistor comprising a floating substrate.

4. The circuit according to claim 1, wherein said first coupling means comprises a single field effect transistor having a source terminal, drain terminal, gate terminal and substrate terminal whereby said substrate terminal is electrically connected to ground via a substantially high resistance.

5. The circuit according to claim 1, wherein said first coupling means comprises a single field effect transistor having a source terminal, drain terminal, gate terminal and substrate terminal whereby said substrate terminal is electrically connected to either said source terminal or said drain terminal via a resistor of sufficiently high value.

6. The circuit according to claim 1, wherein said second coupling means comprises a single field effect transistor comprising a floating substrate.

7. The circuit according to claim 1, wherein said second coupling means comprises a single field effect transistor having a source terminal, drain terminal, gate terminal and substrate terminal whereby said substrate terminal is electrically connected to ground via a substantially high resistance.

8. The circuit according to claim 1, wherein said second coupling means comprises a single field effect transistor having a source terminal, drain terminal, gate terminal and substrate terminal whereby said substrate terminal is electrically connected to either said source terminal or said drain terminal via a resistor of sufficiently high value.

9. The circuit according to claim 1, wherein said control means comprises an inverter circuit adapted to provide control signals to said first coupling means and said second coupling means.

10. The circuit according to claim 1, further comprising an inductance placed in parallel across a series combination of said first coupling means and said second coupling means so as to aid in tuning out the parasitic capacitance of said first coupling means and said second coupling means.

11. The circuit according to claim 1 constructed using RF Complimentary Metal Oxide Semiconductor (CMOS) manufacturing techniques.

12. The circuit according to claim 1 integrated into a RF Complimentary Metal Oxide Semiconductor (CMOS) Integrated Circuit (IC).

13. A Radio Frequency (RF) antenna switch circuit, comprising:

a first field effect transistor (FET) having a drain terminal electrically connected to a transmitter circuit, a source terminal electrically connected to an antenna, a gate terminal and a first substrate terminal, wherein said first substrate terminal is left substantially electrically floating;

a second field effect transistor (FET) having a drain terminal electrically connected to a receiver circuit, a source terminal electrically connected to said antenna, a gate terminal and a second substrate terminal, wherein said second substrate terminal is left substantially electrically floating; and

a control circuit adapted to generate gate control signals applied to the gate terminals of said first FET and second FET so as to establish a signal path from said antenna to either said transmit circuit or said receiver circuit in accordance with a transmit/receive input control signal.

14. The circuit according to claim 13, wherein said signal path comprises a substantially low impedance signal path.

15. The circuit according to claim 13, wherein said first substrate terminal is left completely floating.

16. The circuit according to claim 13, wherein said first substrate terminal is electrically connected to ground via a substantially high resistance.

17. The circuit according to claim 13, wherein said first substrate terminal is electrically connected to either said source terminal or said drain terminal via a resistor of sufficiently high value.

18. The circuit according to claim 13, wherein said second substrate terminal is left completely floating.

19. The circuit according to claim 13, wherein said second substrate terminal is electrically connected to ground via a substantially high resistance.

20. The circuit according to claim 13, wherein said second substrate terminal is electrically connected to either said source terminal or said drain terminal via a resistor of sufficiently high value.

21. The circuit according to claim 13, wherein said control circuit comprises an inverter circuit adapted to generate a first gate control signal applied to the gate terminal of said first FET and a second gate control signal applied to the gate terminal of said second FET in accordance with said transmit/receive input control signal.

22. The circuit according to claim 13, further comprising an inductance placed in parallel across the source terminals of said first FET and said second FET to aid in tuning out the parasitic capacitance of said first FET and said second FET.

23. The circuit according to claim 13 constructed using RF Complimentary Metal Oxide Semiconductor (CMOS) manufacturing techniques.

24. The circuit according to claim 13 integrated into a RF Complimentary Metal Oxide Semiconductor (CMOS) Integrated Circuit (IC).

25. A monolithic integrated circuit, comprising:

a radio Frequency (RF) antenna switch circuit comprising first coupling means for electrically coupling an antenna to a transmitter circuit, second coupling means for electrically coupling said antenna to a receiver circuit, control means for establishing a signal path from said antenna to either said transmit circuit or said receiver circuit in accordance with a transmit/receive switch control signal, wherein said first coupling means and said second coupling means each comprise one or more field effect transistors (FETs) whose substrate terminals are configured to be substantially electrically floating; and

a power amplifier comprising a differential input, an output, a gain control input and an enable input coupled to said transmit/receive switch control signal, said power amplifier operative to generate an amplified output signal at said output from a signal present at said differential input while enabled by said transmit/receive switch control signal.