Scheduling the concurrent testing of multiple cores embedded in an integrated circuit

• US 20030191996A1
• Filed: 07/31/2002
• Published: 10/09/2003
• Est. Priority Date: 04/05/2002
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Tsai, Chien-Chung, Samman, Omer Ghazi, Reddy, Sudhakar Mannapuram, Huang, Yu, Mukherjee, Nilanjan, Cheng, Wu-Tung, Reuter, Paul J., Mustafa, Yahya M. Z.
• Granted Patent: US 6,934,897 B2
• Time in Patent Office: Days
• US Class Current: 714/724
• CPC Class Codes: G01R 31/3193 with comparison between actual response and known fault free response receiver details G01R31/31924

Abstract

Methods are described for scheduling the concurrent testing of multiple cores embedded in an integrated circuit. Test scheduling is performed by formulating the problem as a bin-packing problem and using a modified two-dimensional or three-dimensional bin-packing heuristic. The tests of multiple cores are represented as functions of at least the integrated circuit pins used to test the core and the core test time. The representations may include a third dimension of peak power required to test the core. The test schedule is represented as a bin having dimensions of at least integrated circuit pins and integrated circuit test time. The bin may include a third dimension of peak power. The scheduling of the multiple cores is accomplished by fitting the multiple core test representations into the bin.

Claims

1. A method for optimizing concurrent testing of cores within an integrated circuit comprising:

representing testing of multiple cores, wherein a test of an individual core is represented as a function of at least integrated circuit pins used to test the core and core test time;

representing a test schedule of the integrated circuit as a bin having dimensions of at least integrated circuit pins and integrated circuit test time; and

scheduling the testing of the cores within the integrated circuit by fitting the multiple core test representations into the bin.

2. The method of claim 1, wherein each core test representation comprises a database entry having two parameters including integrated circuit pins used to test the core and core test time.

3. The method of claim 1, wherein the integrated circuit is a system-on-chip.

4. The method of claim 1, wherein the bin dimension of the integrated circuit pins is fixed and scheduling is performed to minimize the bin dimension of the integrated circuit test time.

5. The method of claim 1, wherein the bin dimension of the integrated circuit test time is fixed and scheduling is performed to minimize the bin dimension of the integrated circuit pins.

6. The method of claim 1, wherein the scheduling comprises ensuring that the core test representation fits into the bin by performing a transformation that alters the dimensions of the core test representation.

7. The method of claim 6, wherein the transformation corresponds to accessing memory elements of a scan chain configured to access respective core pins or to concatenating multiple internal scan chains of the core.

8. The method of claim 1, wherein the representing a test of a core is performed for each core and scheduling comprises arranging the core test representations into a list according to core test time.

9. The method of claim 1, wherein the bin comprises multiple bin levels and the representations are fit onto the bin levels.

10. The method of claim 9, wherein the bin levels comprise multiple test sessions.

11. The method of claim 9, wherein each of the bin levels has a height corresponding to the core test time of the first core test representation fit on the level.

12. The method of claim 9, wherein the scheduling comprises fitting a core test representation onto an unfilled bin level having the fewest integrated circuit pins available for testing.

13. The method of claim 9, wherein the scheduling comprises fitting a core test representation onto an unfilled bin level by performing a transformation that alters the dimensions of the representation.

14. The method of claim 1, further comprising:

determining whether a core can be fit without exceeding a peak power constraint; and

if the peak power constraint is exceeded, scheduling the representation to a time when the peak power constraint is satisfied.

15. The method of claim 1, wherein the scheduling comprises:

determining whether a representation from a first bin level can be partially fit into a second bin level; and

partially fitting the representation from the first bin level into the second bin level.

16. The method of claim 1, wherein a weighted cost function is used to determine the relative importance of integrated circuit test time and integrated circuit pins, and wherein the concurrent testing of the cores is optimized according to the function.

17. The method of claim 1, wherein the test of an individual core is further represented as a function of peak power used to test the core, and the test schedule of the integrated circuit is further represented as a function of peak power.

18. The method of claim 17, wherein each core test representation comprises a database entry having three parameters including integrated circuit pins used to test the core, core test time, and peak power used to test the core.

19. The method of claim 17, wherein the representing the testing of multiple cores is performed for each core and scheduling comprises arranging the core test representations into a list according to the product of the integrated circuit pins used to test the core and the core test time.

20. The method of claim 17, wherein the scheduling comprises performing a transformation on the core test representation to alter the core test time by an amount proportional to the peak power of the test schedule.

21. The method of claim 17, wherein the scheduling comprises fitting the core test representation onto a first level of the bin unless the first level is filled or the bin does not have sufficient integrated circuit pins or current peak power available to fit the core test representation.

22. The method of claim 17, wherein the scheduling comprises fitting the core test representation into a sub-bin or a combination of sub-bins that have a sufficient number of integrated circuit pins to fit the core test representation and that minimally increase the integrated circuit test time.

23. The method of claim 17, wherein the core test representation can be scheduled using non-adjacent sub-bins.

24. The method of claim 1, wherein the core test representation and the bin have more than three dimensions.

25. The method of claim 1, wherein at least one of the cores is tested using internally generated test patterns.

26. The method of claim 1 used to:

(a) test an integrated circuit;

(b) design test logic of an integrated circuit;

(c) determine the minimum test time of an integrated circuit;

or

(d) determine the minimum number of test resources required to test an integrated circuit.

27. A computer program encoding the method of claim 1.

28. A computer programmed with the computer program of claim 27.

29. A client computer displaying or using a test schedule compiled by a server computer according to the method of claim 1, the client and server computers communicating via a network.

30. A method for testing multiple cores embedded in an integrated circuit comprising:

representing the testing of multiple cores, wherein each core is represented as at least a two-dimensional function; and

using a bin-packing heuristic to optimize scheduling of the representations.

31. The method of claim 30, wherein each core is represented as a three-dimensional function.

32. The method of claim 30, wherein unscheduled integrated circuit pins can be assigned to test any unscheduled representation.

33. A method for testing multiple cores embedded in an integrated circuit comprising scheduling concurrent testing of multiple cores within the integrated circuit such that the testing occurs using a fixed number of integrated circuit pins, the scheduling comprising:

dividing the testing into multiple test sessions; and

assigning a testing of a core to a test session having fewer unassigned integrated circuit pins than other testing sessions.

34. The method of claim 33, wherein scheduling further comprises assigning the testing of a core to a test session such that a peak power constraint is not exceeded during the test session.

35. The method of claim 33, wherein scheduling further comprises assigning the testing of a core to multiple test sessions in order to reduce the overall test time of the cores.

36. A method for testing multiple cores embedded in an integrated circuit comprising scheduling concurrent testing of multiple cores within the integrated circuit such that the testing occurs within a fixed period of time and an overall number of integrated circuit pins used to test the cores is minimized.