Method and apparatus to facilitate test pattern design for model calibration and proximity correction

• US 20030192015A1
• Filed: 04/04/2002
• Published: 10/09/2003
• Est. Priority Date: 04/04/2002
• Status: Abandoned Application

• Current Assignee: Synopsys Merger Holdings LLC (Synopsys Incorporated)
• Original Assignee: Numerical Technologies Inc. (Synopsys Incorporated)
• Inventors: Liu, Hua-yu
• Application Number:
  US10/116,286
• Publication Number:
  US 20030192015A1
• Time in Patent Office: Days
• US Class Current: 430/5
• CPC Class Codes: G03F 1/44 Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales
• CPC Class Codes: G03F 1/68 Preparation processes not covered by groups G03F1/20 - G03F1/50
• CPC Class Codes: G03F 7/70433 Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
• CPC Class Codes: G03F 7/70441 Optical proximity correction [OPC]
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions

Abstract

By using a test pattern that has been corrected according to an optical model to prepare test wafers, better data can be obtained for calibrating the optical model. As a result: fewer measurements need to be taken from the wafer to calibrate the model and the measurements that are taken are more valuable because they better assist in calibrating the model. Embodiments of the invention include data comprising the corrected test pattern, masks including the corrected test pattern, and methods and apparatuses for using the modified test pattern. Additionally, by taking more measurements closer to the target dimensions, more information is available for performing optical proximity correction of layouts. Another benefit includes increased ease of model accuracy determinations.

Claims

1. A method for using a test pattern to calibrate an optical model related to a manufacturing process for an integrated circuit, comprising:

receiving the test pattern;

performing optical proximity correction on the test pattern using the optical model, thereby creating a partially corrected test pattern;

generating a test mask from the partially corrected test pattern;

fabricating a wafer using the test mask;

measuring features on the wafer to generate a plurality of measurements; and

calibrating the optical model using the plurality of measurements.

2. The method of claim 1, wherein the test pattern includes a plurality of line widths, wherein for each line width the test pattern includes a plurality of line pitches.

3. The method of claim 1, wherein performing optical proximity correction on the test pattern compensates for optical effects involved in the manufacturing process.

4. The method of claim 1, further comprising determining a difference between the partially corrected test pattern and the plurality of measurements for each line width and pitch.

5. The method of claim 4, further comprising comparing an expected line width at a specified pitch with an actual line width at the specified pitch to determine a model error.

6. The method of claim 5, further comprising calibrating the optical model to compensate for resist and etch effects.

7. The method of claim 1, wherein receiving the test pattern includes designing the test pattern with a plurality of lines having different widths and pitches arranged in a grid.

8. A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for using a test pattern to calibrate an optical model related to a manufacturing process for an integrated circuit, the method comprising:

receiving the test pattern;

performing optical proximity correction on the test pattern using the optical model, thereby creating a partially corrected test pattern;

generating a test mask from the partially corrected test pattern;

fabricating a wafer using the test mask;

measuring features on the wafer to generate a plurality of measurements; and

calibrating the optical model using the plurality of measurements.

9. The computer-readable storage medium of claim 8, wherein the test pattern includes a plurality of line widths, wherein for each line width the test pattern includes a plurality of line pitches.

10. The computer-readable storage medium of claim 8, wherein performing optical proximity correction on the test pattern compensates for optical effects involved in the manufacturing process.

11. The computer-readable storage medium of claim 8, the method further comprising determining a difference between the partially corrected test pattern and the plurality of measurements for each line width and pitch.

12. The computer-readable storage medium of claim 11, the method further comprising comparing an expected line width at a specified pitch with an actual line width at the specified pitch to determine a model error.

13. The computer-readable storage medium of claim 12, the method further comprising calibrating the optical model to compensate for resist and etch effects.

14. The computer-readable storage medium of claim 8, wherein receiving the test pattern includes designing the test pattern with a plurality of lines having different widths and pitches arranged in a grid.

15. An apparatus, for using a test pattern to calibrate an optical model related to a manufacturing process for an integrated circuit, comprising:

a receiving mechanism that is configured to receive the test pattern;

an optical proximity correction mechanism that is configured to perform optical proximity correction on the test pattern using the optical model, thereby creating a partially corrected test pattern;

a generating mechanism that is configured to generate a test mask from the partially corrected test pattern;

a fabricating mechanism that is configured to fabricate a wafer using the test mask;

a measuring mechanism that is configured to measure features on the wafer to generate a plurality of measurements; and

a calibrating mechanism that is configured to calibrate the optical model using the plurality of measurements.

16. The apparatus of claim 15, wherein the test pattern includes a plurality of line widths, wherein for each line width the test pattern includes a plurality of line pitches.

17. The apparatus of claim 15, wherein performing optical proximity correction on the test pattern compensates for optical effects involved in the manufacturing process.

18. The apparatus of claim 15, further comprising a difference determining mechanism that is configured to determine a difference between the partially corrected test pattern and the plurality of measurements for each line width and pitch.

19. The apparatus of claim 18, further comprising a comparing mechanism that is configured to compare an expected line width at a specified pitch with an actual line width at the specified pitch to determine a model error.

20. The apparatus of claim 19, wherein the calibrating mechanism is further configured to calibrate the optical model to compensate for resist and etch effects.

21. The apparatus of claim 15, further comprising a designing mechanism that is configured to design the test pattern with a plurality of lines having different widths and pitches arranged in a grid.

22. A system for using a test pattern to calibrate an optical model related to a manufacturing process for an integrated circuit, comprising:

receiving the test pattern;

performing optical proximity correction on the test pattern using the optical model, thereby creating a partially corrected test pattern;

generating a test mask from the partially corrected test pattern;

fabricating a wafer using the test mask;

measuring features on the wafer to generate a plurality of measurements; and

calibrating the optical model using the plurality of measurements.

23. An optical proximity corrected test mask used for calibrating an optical model, comprising a plurality of lines within the optical proximity corrected test mask, wherein the plurality of lines have been partially corrected by an optical proximity correction process to compensate for optical effects.

24. The optical proximity corrected test mask of claim 23, wherein the plurality of lines includes a plurality of line widths.

25. The optical proximity corrected test mask of claim 24, wherein the plurality of lines includes a plurality of line pitches for each of the plurality of line widths.

26. A data set related to an optical proximity corrected test pattern used for calibrating an optical model, comprising:

a plurality of specified line widths;

a plurality of pitches for each of the plurality of specified line widths; and

a plurality of measured line widths, wherein the plurality of measured line widths are measured on a wafer fabricated using the optical proximity corrected test pattern.

27. The data set of claim 26, further comprising a plurality of differences computed by comparing a measured line width of the plurality of measured line widths with a specified line width in the plurality of specified line widths for each line.

28. The data set of claim 27, wherein the plurality of differences is used to calibrate the optical model.

29. An electromagnetic waveform encoding instructions that when executed by a computer cause the computer to perform a method for using a test pattern to calibrate an optical model related to a manufacturing process for an integrated circuit, the method comprising:

receiving the test pattern;

performing optical proximity correction on the test pattern using the optical model, thereby creating a partially corrected test pattern;

generating a test mask from the partially corrected test pattern;

fabricating a wafer using the test mask;

measuring features on the wafer to generate a plurality of measurements; and

calibrating the optical model using the plurality of measurements.