Space-saving packaging of electronic circuits
First Claim
1. A chip stack for forming a circuit of a plurality of integrated circuits formed on discrete substrates, said chip stack comprising:
- a first substrate having first and second faces and a first integrated circuit having one or more interconnection pads formed proximate to said first face of said first integrated circuit, wherein said substrate additionally comprises a plurality of interconnection pathways selected from the set of vias that pass directly through from said first face to said second face of said first substrate, vias that pass in a step-wise manner from said first face to said second face of said first substrate, and vias that pass from one or more of said first integrated circuit interconnection pads to pads at said second surface of said first substrate;
a second substrate having first and second faces and a second integrated circuit having one or more interconnection pads formed proximate to said first face of said second integrated circuit, wherein said substrate additionally comprises a plurality of interconnection pathways selected from the set of vias that pass directly through from said first face to said second face of said second substrate, vias that pass in a step-wise manner from said first face to said second face of said second substrate, and vias that pass from one or more of said second integrated circuit interconnection pads to pads at said second surface of said second substrate; and
wherein one or more of said interconnection pathways from said first substrate to said second substrate enable electrical interconnection between said first integrated circuit to said second integrated circuit when said first and second substrates are vertically stacked.
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Accused Products
Abstract
An apparatus and packaging method for stacking a plurality of integrated circuit substrates which provides interconnection paths through the substrates to simplify electrical connections between the integrated circuits while facilitating minimization of the volume and customization of the three dimensional package size to conform to the available internal space within a housing, e.g., one used in an implantable device where package volume is at a premium. Furthermore, an internal cavity can be created by the stacked formation that is suitable for mounting of a surface mount device, e.g., a crystal or the like.
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Citations
20 Claims
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1. A chip stack for forming a circuit of a plurality of integrated circuits formed on discrete substrates, said chip stack comprising:
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a first substrate having first and second faces and a first integrated circuit having one or more interconnection pads formed proximate to said first face of said first integrated circuit, wherein said substrate additionally comprises a plurality of interconnection pathways selected from the set of vias that pass directly through from said first face to said second face of said first substrate, vias that pass in a step-wise manner from said first face to said second face of said first substrate, and vias that pass from one or more of said first integrated circuit interconnection pads to pads at said second surface of said first substrate;
a second substrate having first and second faces and a second integrated circuit having one or more interconnection pads formed proximate to said first face of said second integrated circuit, wherein said substrate additionally comprises a plurality of interconnection pathways selected from the set of vias that pass directly through from said first face to said second face of said second substrate, vias that pass in a step-wise manner from said first face to said second face of said second substrate, and vias that pass from one or more of said second integrated circuit interconnection pads to pads at said second surface of said second substrate; and
whereinone or more of said interconnection pathways from said first substrate to said second substrate enable electrical interconnection between said first integrated circuit to said second integrated circuit when said first and second substrates are vertically stacked. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method of forming a chip stack comprising:
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forming a first substrate having first and second faces and a first integrated circuit having one or more interconnection pads formed proximate to said first face of said first integrated circuit, wherein said substrate additionally comprises a plurality of interconnection pathways selected from the set of vias that pass directly through from said first face to said second face of said first substrate, vias that pass in a step-wise manner from said first face to said second face of said first substrate, and vias that pass from one or more of said first integrated circuit interconnection pads to pads at said second surface of said first substrate;
forming a second substrate having first and second faces and a second integrated circuit having one or more interconnection pads formed proximate to said first face of said second integrated circuit, wherein said substrate additionally comprises a plurality of interconnection pathways selected from the set of vias that pass directly through from said first face to said second face of said second substrate, vias that pass in a step-wise manner from said first face to said second face of said second substrate, and vias that pass from one or more of said second integrated circuit interconnection pads to pads at said second surface of said second substrate; and
coupling said first and said second substrates together in a vertical stack wherein one or more of said interconnection pathways from said first substrate to said second substrate enable electrical interconnection between said first integrated circuit to said second integrated circuit. - View Dependent Claims (19, 20)
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Specification