Semiconductor device and method of manufacturing the semiconductor device

• US 20030193090A1
• Filed: 05/27/2003
• Published: 10/16/2003
• Est. Priority Date: 09/06/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Inoue, Takashi, Otani, Miharu, Tanaka, Jun, Hotta, Katsuhiko, Suzuki, Yasumichi
• Granted Patent: US 6,967,407 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 21/02118 carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC polymers per se C08G, photoresist per se G03F
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/3122 layers comprising polysiloxane compounds
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 2221/1031 Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05552 : in top view
• CPC Class Codes: H01L 2224/05569 : the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 : the external layer extending out of an opening
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/4824 : Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48599 : Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/73215 : Layer and wire connectors
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 23/585 : comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01093 : Neptunium [Np]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor device capable of high speed operation with a substantially small interlayer capacitance is produced by steps of using an insulating film comprising an organic insulating film and an insulating film composed of an organometallic polymer material as an interlayer insulating film formed by coating, patterning the insulating film in a semi-thermosetting state, etching the organic insulating film as the lower layer by means of the organometallic polymer as a mask, using a plasma gas containing oxygen as the main component, and then conducting ultimate baking treatment of these insulating films.

Claims

1. A semiconductor device comprises a wiring layer and an interlayer insulating film layer, characterized in that the interlayer insulating film layer comprises a first insulating layer composed of an organic insulating film as a lower layer and a second insulating layer composed of an organometallic polymer laid thereon as an upper layer.

3. A semiconductor device according to claim 1, characterized in that the organic insulating film has a relative dielectric constant of not more than 3.5.

4. A semiconductor device according to claim 1, characterized in that the organometallic polymer has a relative dielectric constant of less than 4.0.

6. A semiconductor device according to claim 1, characterized in that at least one of the first insulating layer and the second insulating layer is formed by a coating method.

8. A semiconductor device according to claim 1, characterized in that the second insulating layer has a thickness as large as or smaller than that of the first insulating layer.

9. A semiconductor device according to claim 1, characterized in that the first insulating layer composed of an organic insulating film is made from a thermosetting resin and is formed by baking.

10. A semiconductor device according to claim 1, characterized in that the second insulating layer composed of an organometallic polymer is formed by exposure to a plasma gas containing oxygen as the main component and then by baking.

12. A semiconductor device according to claim 1, characterized in that the first insulating layer has an opening and the opening is formed by dry etching by means of the second insulating layer as a mask, using a plasma gas containing oxygen as the main component.

13. A semiconductor device according to claim 1, characterized in that the organometallic polymer has organic functional groups and the organic functional groups are decomposed and removed by dry etching, using a plasma gas containing oxygen as the main component, and by heat treatment.

15. A semiconductor device according to claim 1, characterized in that the second insulating layer has a film hardness improved by dry etching, using a plasma gas containing oxygen as the main component, and by heat treatment.

17. A semiconductor device according to claim 1, characterized in that the organometallic polymer is a ladder silicone-based polymer.

19. A semiconductor device according to claim 17, characterized in that the ladder silicone-based polymer is a polymer material having a molecular structure represented by the following formula (I):

21. A semiconductor device according to claim 17, characterized in that the ladder silicone-based polymer is a polymer material having a molecular structure represented by the following formula (II):

23. A semiconductor device according to claim 1, characterized in that the second insulating layer is composed of a photo-sensitive resin material comprising a ladder silicone-based polymer and a photo-sensitizer.

2. A semiconductor device comprising a wiring layer and an interlayer insulating film layer, characterized in that the interlayer insulating film layer is a second insulating layer composed of an organometallic polymer.

5. A semiconductor device according to claim 2, characterized in that the organometallic polymer has a relative dielectric constant of less than 4.0.

7. A semiconductor device acocrding to claim 2, characterized in that the second insulating layer composed of an organometallic polymer is formed by a coating method.

11. A semiconductor device according to claim 2, characterized in that the second insulating layer composed of an organometallic polymer is formed by exposure to a plasma gas containing oxygen as the main component and then by baking.

14. A semiconductor device according to claim 2, characterized in that the organometallic polymer has organic functional groups and the organic functional groups are decomposed and removed by dry etching, using a plasma gas decomposed oxygen as the main component, and by heat treatment.

16. A semiconductor device according to claim 2, characterized in that the second insulating layer has a film hardness improved by dry etching, using a plasma gas containing oxygen as the main component, and by heat treatment.

18. A semiconductor device according to claim 2, characterized in that the organometallic polymer is a ladder silicone-based polymer.

20. A semiconductor device according to claim 18, characterized in that the ladder silicone-based polymer is a polymer material having a molecular structure represented by the following formula (I):

22. A semiconductor device according to claim 18, characterized in that the ladder silicone-based polymer is a polymer material having a molecular structure represented by the following formula (II):

24. A semiconductor material according to claim 2, characterized in that the second insulating layer is composed of a photo-sensitive material comprising a ladder silicone-based polymer and a photo-sensitizer.

25. An electronic circuit device comprising a wiring layer and an interlayer insulating film layer, characterized in that the interlayer insulating film layer comprises a first insulating layer composed of an organic insulating film as a lower layer and a second insulating layer composed of an organometallic polymer laid thereon as an upper layer.

26. A process for producing a semiconductor device, characterized by comprising a step of applying an organic insulating film material to a substrate, thereby forming a first insulating layer, a step of applying an organometallic polymer material to the first insulating layer, thereby forming a second insulating layer, a step of forming an opening-forming resist pattern on the second insulating layer, a step of forming an opening in the second insulating layer by means of the resist pattern as a mask, a step of forming an opening in the first insulating layer by means of the resist pattern and the second insulating layer as a mask by dry etching, while removing the resist, and a step of baking the first insulating layer and the second insulating layer.

27. A process for producing the semiconductor device according to claim 26, characterized in that the organometallic polymer material is a ladder silicone-based polymer material having a molecular structure represented by the following formula (II):

32. A process for producing a semiconductor device according to claim 26, characterized in that the step of forming an opening in the first insulating layer or the second insulating layer is at least one of a step of forming a contact hole and a step of forming a wiring trench.

35. A process for producing a semiconductor device according to claim 26, characterized in that after the first insulating layer is baked in a temperature range below 350°

C., the opening is formed in the first insulating layer.

38. A process for producing a semiconductor device according to claim 26, characterized in that after the opening is formed in the first insulating layer, the first insulating layer is baked in a temperature range of not less than 350°

C.

41. A process for producing a semiconductor device according to claim 26, characterized in that the opening is formed in the first insulating layer by dry etching, using a plasma gas containing oxygen as the main component.

42. A process for producing a semiconductor device according to claim 26, characterized in that the second insulating layer has a thickness as large as or smaller than that of the first insulating layer.

43. A process for producing a semiconductor device according to claim 26, characterized in that the second insulating layer is exposed to a plasma gas containing oxygen as the main component and then subjected to baking treatment.

44. A process for producing a semiconductor device according to claim 26, characterized in that the opening is formed in the first by dry etching by means of the second insulating layer as a mask, using a plasma gas containing oxygen as the main composed.

45. A process for producing a semiconductor device according to claim 26, characterized in that the organometallic polymer material has organic functional groups, and the organic functional groups are decomposed and removed by dry etching, using a plasma gas containing oxygen as the main component, and by heat treatment.

46. A process for producing a semiconductor device according to claim 26, characterized in that the film hardness of the second insulating layer is improved by subjecting the second insulating layer to dry etching, using a plasma gas containing oxygen as the main component, and to heat treatment.

28. A process for producing a semiconductor device, characterized by a step of applying an organic insulating film material to a substrate, thereby forming a first insulating layer, a step of applying an organometallic polymer material to the first insulating layer, thereby forming a second insulating layer, a step of forming an opening-forming resist pattern on the second insulating layer, while forming an opening in the second insulating layer, a step of forming an opening in the first insulating layer by dry etching, while removing the resist, and a step of baking the first insulating layer and the second insulating layer.

29. A process for producing a semiconductor device according to claim 28, characterized in that the organometallic polymer material is a ladder silicone-based polymer material having a molecular structure represented by the following formula (I):

33. A process for producing a semiconductor device according to claim 28, characterized in that the step of forming an opening in the first insulating layer or the second insulating layer is at least one of a step of forming a contact hole and a step of forming a wiring trench.

36. A process for producing a semiconductor device according to claim 28, characterized in that after the first insulating layer is baked in a temperature range below 350°

C., the opening is formed in the first insulating layer.

39. A process for producing a semiconductor device according to claim 28, characterized in that after the opening is formed in the first insulating layer, the first insulating layer is baked in a temperature range of not less than 350°

C.

30. A process for forming a semiconductor device, characterized by comprising a step of applying an organic insulating film material to a substrate, thereby forming a first insulating layer, a step of applying an organometallic polymer material to the first insulating layer, thereby forming a second insulating layer, a step of forming an opening in the second insulating layer, a step of forming an opening in the first insulating layer by dry etching by means of the second insulating layer as a mask, and a step of baking the first insulating layer and the second insulating layer.

31. A process for forming a semiconductor device according to claim 30, characterized in that the organometallic polymer material is a photo-sensitive resin material comprising a ladder silicone-based polymer material having alkali-soluble group-containing organic functional groups and a photo-sensitizer.

34. A process for producing a semiconductor device according to claim 30, characterized in that the step of forming an opening in the first insulating layer or the second insulating layer is at least one of a step of forming a contact hole and a step of forming a wiring trench.

37. A process for producing a semiconductor device according to claim 30, characterized in that after the first insulating layer is baked in a temperature range below 350°

C., the opening is formed in the first insulating layer.

40. A process for producing a semiconductor device according to claim 30, characterized in that after the opening is formed in the first insulating layer, the first insulating layer is baked in a temperature range of not less than 350°

C.

47. A semiconductor memory device, comprising a memory device-containing semiconductor substrate, an insulating interlayer laid on the semiconductor substrate, an upper wiring layer and a wiring material, provided with a partition wall surrounding device peripheral region to prevent moisture absorption and permeation through the peripheral region (the protection wall will be hereinafter referred to as guard ring), characterized in that the insulating interlayer comprises an insulating film composed of an organic insulating film as a lower layer and an insulating film composed of a ladder silicone-based polymer material laid thereon as an upper layer, one end of the guard ring provided in the outermost peripheral region of the memory device is connected to the upper wiring layer, while the other end thereof is embedded in the semiconductor substrate.

48. A semiconductor device comprising a MOS transistor-containing semiconductor substrate, and a BPSG layer, a wiring layer, an insulating interlayer and a protective film, successively formed on the semiconductor substrate, characterized in that an electroconductive plug provided through the BPSG layer and insulating interlayer is connected to the semiconductor substrate through the wiring layer, the insulating interlayer comprises an insulating film composed of an organic insulating film as a lower layer and an insulating film composed of a ladder silicone-based polymer material laid thereon as an upper layer, and the protective film is provided so as to enclose the edges of the BPSG layer and the insulating interlayer.

49. A semiconductor device according to claim 48, characterized in that the edge of the protective film is embedded in the semiconductor substrate.

50. A semiconductor device according to claim 48, characterized in that the protective film is a silicon nitride film.