QPSK and 16 QAM self-generating synchronous direct downconversion demodulator

• US 20030193365A1
• Filed: 04/15/2002
• Published: 10/16/2003
• Est. Priority Date: 04/15/2002
• Status: Active Grant

• Current Assignee: The Boeing Co.
• Original Assignee: The Boeing Co.
• Inventors: Loheit, Kurt, Cooper, James D., Burk, Leah N., Kubasek, Suzanne E.
• Granted Patent: US 6,717,462 B2
• Time in Patent Office: Days
• US Class Current: 329/304
• CPC Class Codes: H03D 3/247 using a controlled phase shifter in general H03L7/081

Abstract

A system for recovering and demodulating a carrier includes a carrier recovery loop and a data detector. The carrier recovery loop receives the carrier as an input and produces a recovered carrier at a frequency approximately equal to that of the carrier. The carrier recovery loop includes a downconverting mixer, a ×5 multiplier, a ×4 multiplier, and a phase locked loop. The downconverting mixer receives the carrier input, and the phase locked loop provides a VCO reference frequency through the ×5 multiplier to the downconverting mixer, which provides a frequency shifted signal. The frequency shifted signal is passed through the ×4 multiplier as input to the phase locked loop. The data detector receives the carrier and the recovered carrier as inputs and uses the recovered carrier to demodulate the carrier and detect I channel data and Q channel data.

Claims

1. A system for recovering and demodulating a carrier, comprising:

a carrier recovery loop receiving the carrier as an input, said carrier recovery loop producing a recovered carrier at a frequency approximately equal to that of the carrier; and

a data detector, said data detector receiving the carrier and said recovered carrier as inputs and using said recovered carrier to demodulate the carrier and detect I channel data and Q channel data.

2. The system of claim 1 wherein said carrier recovery loop comprises a downconverting mixer, a ×

5 multiplier, a ×

4 multiplier, and a phase locked loop, and wherein said downconverting mixer receives the carrier as an input, said phase locked loop provides a VCO reference frequency through said ×

5 multiplier to said downconverting mixer, said downconverting mixer provides a frequency shifted signal, and said frequency shifted signal is passed through said ×

4 multiplier to said phase locked loop.

3. The system of claim 1 wherein said phase locked loop comprises a phase detector, a loop filter, a VCO, and a ×

4 multiplier, and wherein said VCO provides a VCO reference frequency to said ×

4 multiplier, said ×

4 multiplier produces an upconverted VCO reference frequency to provide said recovered carrier, said phase detector compares an upconverted frequency shifted signal to said upconverted VCO reference frequency and drives said loop filter, and said loop filter provides a control voltage to said VCO.

4. The system of claim 2 wherein said frequency shifted signal has a frequency and the carrier has a carrier frequency, said frequency of said frequency shifted signal is approximately one quarter said carrier frequency, and said ×

4 multiplier upconverts said frequency shifted signal by a factor of four.

5. The system of claim 2 wherein the carrier has a carrier frequency, said VCO reference frequency is approximately one quarter said carrier frequency, and said ×

5 multiplier upconverts said VCO reference frequency by a factor of five.

6. The system of claim 1, further comprising a phase adjuster, wherein said recovered carrier is passed through said phase adjuster to provide a phase adjusted recovered carrier and said data detector receives the carrier and said phase adjusted recovered carrier as inputs.

7. The system of claim 6 wherein the carrier and said phase adjusted recovered carrier each have a phase and said phase adjuster matches said phase of said phase adjusted recovered carrier to said phase of the carrier.

8. The system of claim 1 wherein said data detector comprises a first mixer, said first mixer using the carrier and said phase adjusted recovered carrier to detect said I channel data.

9. The system of claim 1 wherein said data detector comprises a second mixer and a phase shifter, said phase adjusted recovered carrier feeding to said second mixer via said phase shifter, and said second mixer using the carrier and said phase adjusted recovered carrier to detect said Q channel data.

10. The system of claim 1 wherein said data detector comprises a first post detection filter, and an output of said first mixer is passed through said first post detection filter to reproduce said I channel data.

11. The system of claim 1 wherein said data detector comprises a second post detection filter, and an output of said second mixer is passed through said second post detection filter to reproduce said Q channel data.

12. The system of claim 1 wherein said system is fabricated using MMIC.

13. The system of claim 1 wherein said system is fabricated using ASIC.

14. A system for recovering and demodulating a carrier, comprising:

a carrier recovery loop receiving the carrier as an input, said carrier recovery loop producing a recovered carrier at a frequency approximately equal to that of the carrier;

wherein said carrier recovery loop comprises a downconverting mixer, a ×

5 multiplier, a ×

4 multiplier, and a phase locked loop, and wherein said downconverting mixer receives the carrier as an input, said phase locked loop provides a VCO reference frequency through said ×

5 multiplier to said downconverting mixer, said downconverting mixer provides a frequency shifted signal, and said frequency shifted signal is passed through said ×

4 multiplier to said phase locked loop; and

a data detector, said data detector receiving the carrier and said recovered carrier as inputs and using said recovered carrier to demodulate the carrier and detect I channel data and Q channel data.

15. The system of claim 14 wherein said phase locked loop comprises a phase detector, a loop filter, a VCO, and a second ×

4 multiplier, and wherein said VCO provides a VCO reference frequency to said second ×

4 multiplier, said second ×

4 multiplier produces an upconverted VCO reference frequency to provide said recovered carrier, said phase detector compares an upconverted frequency shifted signal to said upconverted VCO reference frequency and drives said loop filter, and said loop filter provides a control voltage to said VCO.

16. The system of claim 14 wherein:

the carrier has a carrier frequency and said frequency shifted signal has a frequency,

said frequency of said frequency shifted signal is approximately one quarter said carrier frequency, and said ×

4 multiplier upconverts said frequency shifted signal by a factor of four; and

said VCO reference frequency is approximately one quarter said carrier frequency, and said ×

5 multiplier upconverts said VCO reference frequency by a factor of five.

17. The system of claim 14, further comprising a phase adjuster, wherein said recovered carrier is passed through said phase adjuster to provide a phase adjusted recovered carrier and said data detector receives the carrier and said phase adjusted recovered carrier as inputs.

18. The system of claim 14 wherein the carrier and said phase adjusted recovered carrier each have a phase and said phase adjuster matches said phase of said phase adjusted recovered carrier to said phase of the carrier.

19. The system of claim 14 wherein said data detector comprises a first mixer, said first mixer using the carrier and said phase adjusted recovered carrier to detect said I channel data.

20. The system of claim 14 wherein said data detector comprises a second mixer and a phase shifter, said phase adjusted recovered carrier feeding to said second mixer via said phase shifter, and said second mixer using the carrier and said phase adjusted recovered carrier to detect said Q channel data.

21. The system of claim 14 wherein said data detector comprises a first post detection filter, and an output of said first mixer is passed through said first post detection filter to reproduce said I channel data.

22. The system of claim 14 wherein said data detector comprises a second post detection filter, and an output of said second mixer is passed through said second post detection filter to reproduce said Q channel data.

23. The system of claim 14 wherein said system is fabricated using MMIC.

24. The system of claim 14 wherein said system is fabricated using ASIC.

25. A system for recovering and demodulating a carrier, comprising:

a carrier recovery loop receiving the carrier as an input, said carrier recovery loop producing a recovered carrier at a frequency approximately equal to that of the carrier;

wherein said carrier recovery loop comprises a downconverting mixer, a ×

5 multiplier, a first ×

4 multiplier, and a phase locked loop, and wherein said downconverting mixer receives the carrier as an input, said phase locked loop provides a VCO reference frequency through said ×

5 multiplier to said downconverting mixer, said downconverting mixer provides a frequency shifted signal, and said frequency shifted signal is passed through said first ×

4 multiplier to said phase locked loop,

wherein said phase locked loop comprises a phase detector, a loop filter, a VCO, and a second ×

4 multiplier, and wherein said VCO provides said VCO reference frequency to said second ×

4 multiplier, said second ×

4 multiplier produces an upconverted VCO reference frequency to provide said recovered carrier, said phase detector compares an upconverted frequency shifted signal to said upconverted VCO reference frequency and drives said loop filter, and said loop filter provides a control voltage to said VCO, and

wherein the carrier has a carrier frequency and said frequency shifted signal has a frequency, said frequency of said frequency shifted signal is approximately one quarter said carrier frequency, and said first ×

4 multiplier upconverts said frequency shifted signal by a factor of four; and

said VCO reference frequency is approximately one quarter said carrier frequency, and said ×

5 multiplier upconverts said VCO reference frequency by a factor of five;

a phase adjuster, wherein said recovered carrier is passed through said phase adjuster to provide a phase adjusted recovered carrier, and wherein the carrier and said phase adjusted recovered carrier each have a phase and said phase adjuster matches the phase of said phase adjusted recovered carrier to the phase of the carrier; and

a data detector, said data detector receiving the carrier and said phase adjusted recovered carrier as inputs and using said phase adjusted recovered carrier to demodulate the carrier and detect I channel data and Q channel data,

wherein said data detector comprises a first mixer, said first mixer using the carrier and said phase adjusted recovered carrier to detect said I channel data, said data detector comprises a second mixer and a phase shifter, said phase adjusted recovered carrier feeding to said second mixer via said phase shifter, and said second mixer using the carrier and said phase adjusted recovered carrier to detect said Q channel data, said data detector comprises a first post detection filter, an output of said first mixer being passed through said first post detection filter to reproduce said I channel data, and said data detector comprises a second post detection filter, an output of said second mixer being passed through said second post detection filter to reproduce said Q channel data.

26. A method for demodulating a carrier, comprising steps of:

down converting the carrier to produce a frequency shifted signal;

feeding said frequency shifted signal to a phase locked loop;

using said phase locked loop to produce a recovered carrier, said recovered carrier having a frequency approximately equal to that of the carrier, and said recovered carrier having a phase;

adjusting said phase of said recovered carrier to produce a phase adjusted recovered carrier;

providing the carrier and said phase adjusted recovered carrier to a data detector; and

demodulating the carrier and detecting I channel data and Q channel data using said data detector.

27. The method of claim 26 wherein said step of using a phase locked loop further comprises steps of:

detecting a phase of said frequency shifted signal relative to a VCO reference frequency to drive a loop filter to provide a control voltage to a VCO; and

controlling said VCO with said control voltage to provide said VCO reference frequency.

28. The method of claim 27 wherein:

said frequency shifted signal has a frequency and the carrier has a carrier frequency,

said frequency of said frequency shifted signal is approximately one quarter said carrier frequency,

said VCO reference frequency is approximately one quarter said carrier frequency, and

said frequency shifted signal is upconverted to approximately the carrier frequency and said VCO reference frequency is upconverted to approximately the carrier frequency before said step of detecting a phase.

29. The method of claim 28 wherein said step of downconverting the carrier further comprises steps of:

upconverting said VCO reference frequency by a factor of five to produce a signal at a frequency of approximately 5/4 times said carrier frequency; and

mixing said signal at a frequency of approximately 5/4 times said carrier frequency with the carrier.

30. The method of claim 26 wherein the carrier and said phase adjusted recovered carrier each have a phase, and said adjusting step comprises matching the phase of said phase adjusted recovered carrier to the phase of the carrier.

31. The method of claim 26 wherein said data detector comprises a first mixer, and said first mixer uses the carrier and said phase adjusted recovered carrier to detect said I channel data.

32. The method of claim 26 wherein said data detector comprises a second mixer and a phase shifter, and said phase adjusted recovered carrier is fed to said second mixer via said phase shifter, and said second mixer uses the carrier and said phase adjusted recovered carrier to detect said Q channel data.

33. The method of claim 26 wherein said data detector comprises a first post detection filter, and an output of said first mixer is passed through said first post detection filter to reproduce said I channel data.

34. The method of claim 26 wherein said data detector comprises a second post detection filter, and an output of said second mixer is passed through said second post detection filter to reproduce said Q channel data.