Single substrate camera device with CMOS image sensor

• US 20030193597A1
• Filed: 04/15/2003
• Published: 10/16/2003
• Est. Priority Date: 01/28/1994
• Status: Active Grant

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Nixon, Robert, Fossum, Eric R.
• Granted Patent: US 7,369,166 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: G11C 19/282 with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
• CPC Class Codes: G11C 19/285 Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14656 Overflow drain structures
• CPC Class Codes: H01L 27/14843 Interline transfer
• CPC Class Codes: H01L 27/1485 Frame transfer
• CPC Class Codes: H01L 27/14887 Blooming suppression
• CPC Class Codes: H01L 31/02162 for filtering or shielding light, e.g. multicolour filters for photodetectors
• CPC Class Codes: H01L 31/0232 Optical elements or arrangements associated with the device H01L31/0236 takes precedence; for photovoltaic cells H01L31/054; for photovoltaic modules H02S40/20
• CPC Class Codes: H04N 23/10 for generating image signals from different wavelengths
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 : Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/77 : Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/771 : comprising storage means other than floating diffusion

Abstract

Single substrate device is formed to have an image acquisition device and a controller. The controller on the substrate controls the system operation.

Claims

1. A single chip camera device, comprising:

a substrate;

an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS and both integrated in said substrate;

said image acquisition portion including an array of active pixel type photoreceptors integrated in said substrate, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor;

said control portion including a signal controlling device integrated in said substrate, controlling said photoreceptors to output their signals,

said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors.

2. A camera device as in claim 1 wherein said array of photoreceptors are controlled to output an entire row of said photoreceptors simultaneously.

3. A camera device as in claim 1, wherein said photoreceptors include photodiodes.

4. A camera device as in claim 1, wherein said photoreceptors include photogates.

5. A single chip camera device, comprising;

a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;

said image acquisition portion integrated in said substrate including an array of photoreceptors said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time,

said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors.

6. A camera device as in claim 5, wherein said signal controlling device includes a column-parallel read out device, which reads out a row of said photoreceptors at substantially the same time.

7. A camera device as in claim 5, wherein said signal controlling device includes a column selector allowing selection of a desired column for read out, and a row selector which allows selection of a desired row for read out.

8. A camera device as in claim 5, wherein said array of photoreceptors includes an active pixel sensor, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor.

9. A camera device as in claim 8, wherein said readout amplifier is preferably within and/or associated with one element of the array.

10. A camera device as in claim 8, wherein said photoreceptors are photodiodes.

11. A camera device as in claim 8, wherein said photoreceptors are photogates.

12. A single chip camera device, comprising:

a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;

said image acquisition portion including an array of photoreceptors arranged in rows and columns;

a charge storage element, associated with each said column;

said control portion including a signal controlling device, controlling said photoreceptors to output their signals, and a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors;

said control portion including common logic elements to control all pixels on a selected row to sample said all pixels onto said charge storage elements substantially simultaneously.

13. A device as in claim 12, wherein said logic elements control said pixels to first sample a reset level of each said row, and then to sample a charged level of said charge storage elements to produce information indicating a correlated signal indicative of a difference therebetween.

14. A device as in claim 12, wherein said control portion includes a plurality of column selection p-channel transistors, respectively associated with each column, said transistors being turned on to sample a column.

15. A device as in claim 12, wherein there is one of said charge storage elements associated with each of said columns.

16. A device as in claim 12, wherein there are two of said charge storage elements associated with each of said columns.

17. A camera device as in claim 12, wherein said array of photoreceptors includes an active pixel sensor, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor.

18. A camera device as in claim 17, wherein said readout amplifier is preferably within and/or associated with one element of the array.

19. A camera device as in claim 17, wherein said photoreceptors are photodiodes.

20. A camera device as in claim 17, wherein said photoreceptors are photogates.