Network thread scheduling

• US 20030195916A1
• Filed: 04/15/2002
• Published: 10/16/2003
• Est. Priority Date: 04/15/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Putzolu, David M.
• Granted Patent: US 7,054,950 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/552 by ensuring the integrity of packets received through redundant connections

Abstract

A method, system or product that identifies data packets with a common characteristic and routes all data packets having the same characteristic to the same thread of execution or device in a system which processes data packets in parallel.

Claims

1. A method comprising:

performing a task on data packets in parallel using multiple devices; and

routing data packets, which appear in an order in a series of data packets, to respective ones of the multiple devices in a manner to preserve the order of at least some of the packets that are related by a common characteristic.

2. The method of claim 1 in which the routing includes applying a function to the data packets to produce a data packet identifier for each data packet, and sending each data packet having a given data packet identifier to the same device.

3. The method of claim 2, further comprising storing each data packet identifier.

4. The method of claim 3, wherein each data packet identifier is stored as an addendum to each data packet.

5. The method of claim 1 wherein the common characteristic comprises the end-host to which the packets are bound.

6. The method of claim 1 wherein the common characteristic comprises the source host from which the data packets are coming.

7. The method of claim 2 wherein the function applied to each data packet comprises a mask of at least one bit of a destination Internet Protocol address associated with each data packet.

8. The method of claim 2 wherein the function applied to each data packet comprises a mask of at least one bit of the Destination Media Access Control (DMAC) address associated with each packet in an Ethernet-based network.

9. The method of claim 2 wherein the function applied to each data packet comprises a hash of at least one bit of the label associated with each packet provided by a label edge router in a Multi-Protocol Label Switching-based network.

10. The method of claim 2 wherein the function applied to each data packet comprises a hash of at least one bit of the Virtual Path Identifier (VPI) associated with each packet in a network using Asynchronous Transfer Mode (ATM) technology.

11. The method of claim 1 wherein the multiple devices comprise microengines within a network processor.

12. The method of claim 1 wherein the multiple devices comprise multiple application specific integrated circuits.

13. A method comprising:

receiving a sequence of data packets;

applying a function to the data packets to generate information that classifies the packets into groups such that the sequential order of packets in each of the groups is to be maintained; and

storing the classification information for later use.

14. The method of claim 13, further comprising:

performing a task on the data packets in parallel using multiple devices;

accessing the classification information; and

routing the data packets classified in a given group to the same device.

15. The method of claim 14, wherein the function comprises a mask of the destination address associated with each packet.

16. The method of claim 14, wherein the function comprises a hash of the source address associated with each packet.

17. The method of claim 13, wherein the classification information is stored as an addendum to each data packet.

18. The method of claim 14, wherein the multiple devices comprise microengines of a network processor.

19. A system comprising:

a processor configured to process data packets in at least two threads of execution simultaneously; and

a multi-threading management system configured to identify data packets with a common characteristic and route all data packets having the same characteristic to the same thread.

20. The system of claim 19 wherein the processor comprises an application specific integrated circuit.

21. The system of claim 19 wherein the processor comprises a network processor.

22. The system of claim 19 wherein the multi-threading management system is stored on a computer readable medium.

23. The system of claim 20 wherein the multi-threading management system is hard wired into the application specific integrated circuit.

24. The system of claim 19, wherein the multi-threading management system further comprises a storage device.

25. The system of claim 19, wherein the common characteristic comprises the end host to which the packets are bound.

26. The system of claim 19, wherein the common characteristic comprises the source of from where the packets are coming.

27. A computer program product residing on a computer readable medium having instructions stored thereon that, when executed by the processor, cause that processor to:

apply a function to data packets to generate a data packet identifier; and

route all data packets having the same identifier to the same thread of execution in a multi-threaded processor.

28. The computer program product of claim 27, further causing the processor to:

store the packet identifier for each data packet.

29. The computer program product of claim 28, wherein the function to produce a data packet identifier comprises a mask of at least one bit of information associated with each data packet.

30. The computer program of claim 29, wherein the mask comprises at least one bit of the destination Internet Protocol address of each packet.

31. The computer program of claim 29, wherein the mask comprises at least one bit of the Virtual Channel Identifier in a network using Asynchronous Mode Transfer technology.

32. The computer program product of claim 27, wherein the function comprises a hash of at least one bit of information associated with each data packet.

33. The computer program product of claim 27 wherein the multi-threaded processor comprises a network processor.

34. The computer program product of claim 27 wherein the multi-threaded processor comprises a plurality of application specific integrated circuits.