Conditional read and invalidate for use in coherent multiprocessor systems

• US 20030195939A1
• Filed: 04/16/2002
• Published: 10/16/2003
• Est. Priority Date: 04/16/2002
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Edirisooriya, Samatha J., Jamil, Sujat, Miner, David E., Tu, Steven J., Nguyen, Hang T., OʼBleness, R. Frank
• Application Number:
  US10/123,401
• Publication Number:
  US 20030195939A1
• Time in Patent Office: Days
• US Class Current: 709/212
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means

Abstract

A conditional read and invalidate operation for use in coherent multiprocessor systems is disclosed. A conditional read and invalidate request may be sent via an interconnection network from a first processor that requires exclusive access to a cache block to a second processor that requires exclusive access to the cache block. Data associated with the cache block may be sent from the second processor to the first processor in response to the conditional read and invalidate request and a determination that the cache block is associated with a state of a cache coherency protocol.

Claims

1. A method of controlling a cache block, comprising:

sending a conditional read and invalidate request from a first agent associated with the cache block to a second agent associated with the cache block; and

transferring data between the first and second agents in response to the conditional read and invalidate request.

2. The method of claim 1, wherein sending the conditional read and invalidate request from the first agent associated with the cache block to the second agent associated with the cache block includes sending the conditional read and invalidate request from a first processor requiring exclusive access to the cache block to a second processor requiring exclusive access to the cache block.

3. The method of claim 1, wherein transferring data between the first and second agents in response to the conditional read and invalidate request includes sending updated cache information from the second agent to the first agent.

4. The method of claim 2, wherein transferring data between the first and second agents in response to the conditional read and invalidate request includes sending updated cache information from the second agent to the first agent.

5. The method of claim 1, further including generating one of a HIT and a HITM signal in response to the conditional read and invalidate request.

6. The method of claim 1, further including setting a state associated with the cache block and the second agent to invalid in response to the conditional read and invalidate request.

7. A method of controlling a cache block for use with a cache coherency protocol, the method comprising:

sending a conditional read and invalidate request via an interconnection network from a first processor that requires exclusive access to the cache block to a second processor that requires exclusive access to the cache block; and

sending data associated with the cache block from the second processor to the first processor in response to (a) the conditional read and invalidate request and (b) a determination that a predefined state of the cache coherency protocol is associated with the cache block in the second processor.

8. The method of claim 7, further including generating one of a HIT and a HITM signal in the second processor in response to the determination that the predefined state of the cache coherency protocol is associated with the cache block in the second processor.

9. The method of claim 7, further including associating an invalid state with the cache block in the second processor after sending the data associated with the cache block in the second from the second processor to the first processor.

10. The method of claim 7, wherein the predefined state is one of a shared state, a modified state and an owned state.

11. The method of claim 7, wherein sending the data associated with the cache block from the second processor to the first processor includes sending an updated version of the cache block data from the second processor to the first processor.

12. The method of claim 7, further including generating a back off request in response to an agent requesting exclusive access to the cache block.

13. A method of controlling data transfers between first and second caches, the method comprising:

generating at a first time a first conditional read and invalidate request in response to a request for exclusive access to a cache block within the first cache;

generating at a second time prior to the first time a second conditional read and invalidate request in response to a request for exclusive access to the cache block within the second cache; and

transferring data from the first cache to the second cache upon reception of the second conditional read and invalidate request by an agent associated with the first cache and a determination by the agent that a state of the cache block within the first cache is one of a shared state, an owned state and a modified state.

14. The method of claim 13, further including generating one of a HIT and a HITM signal in response to the determination by the agent that the state of the cache block within the first cache is one of the shared, owned and modified states.

15. The method of claim 13, further including associating an invalid state with the cache block within the first cache after transferring the data from the first cache to the second cache.

16. The method of claim 13, wherein transferring the data from the first cache to the second cache includes sending an updated version of the cache block data from the first cache to the second cache.

17. The method of claim 13, wherein the first and second times occur substantially simultaneously.

18. A processor for use in a multiprocessor system, the processor comprising:

a cache; and

a cache controller to generate a first conditional read and invalidate request in response to the processor requiring exclusive access to a block within the cache and to send data to another processor in response to (a) reception of a second conditional read and invalidate request from the other processor and (b) a determination that a state of the block within the cache is one of a shared state, an owned state and a modified state.

19. The processor of claim 18, wherein the cache controller generates one of a HIT and a HITM in response to the determination that the state of the block within the cache is one of the shared, owned and modified states.

20. The processor of claim 18, wherein the cache controller associates an invalid state with the cache block after sending the data to the other processor.

21. The processor of claim 18, wherein the cache controller sends an updated version of the cache block data to the other processor.

22. A multiprocessor system, comprising:

a first processor having a first cache and a first cache controller;

a second processor having a second cache and second cache controller, wherein the first and second cache controllers generate respective conditional read and invalidate requests in response to requests for exclusive access to cache blocks within the first and second caches; and

an interconnection network that communicatively couples the first and second processors.

23. The multiprocessor system of claim 22, wherein the first and second cache controllers generate HIT and HITM signals on the interconnection network in response to reception of the conditional read and invalidate requests.

24. The multiprocessor system of claim 22, further including a system memory communicatively coupled to the first and second processors via the interconnection network.

25. The multiprocessor system of claim 24, further including a memory controller coupled to the interconnection network.