Method and apparatus for communicating securely with a token
First Claim
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1. An apparatus comprising:
- a processor coupled to a first bus to issue a trusted request;
a token; and
a chipset coupled to the processor by the first bus, said chipset coupled to the token by a second bus, said chipset to decode the trusted request from the processor and to forward the trusted request to the token, said chipset to prevent the trusted request from being echoed on one or more busses other than the second bus.
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Abstract
A method and apparatus to communicate with a token using a previously reserved binary number in the start field of a cycle, wherein the cycle is not echoed on any bus other than the bus through which the communication is received.
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Citations
32 Claims
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1. An apparatus comprising:
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a processor coupled to a first bus to issue a trusted request;
a token; and
a chipset coupled to the processor by the first bus, said chipset coupled to the token by a second bus, said chipset to decode the trusted request from the processor and to forward the trusted request to the token, said chipset to prevent the trusted request from being echoed on one or more busses other than the second bus. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprising:
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sending by a processor a request to a chipset;
decoding by the chipset the request received from the processor; and
forwarding the request via a bus to a token using a code, said code selected such that other devices on the bus ignore the request. - View Dependent Claims (9, 10)
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11. A chipset comprising:
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a first interface logic to receive from a processor a trusted request via a first bus;
a second interface logic coupled to a token via a second bus;
a decoding logic coupled to the first interface logic and the second interface logic, said first interface logic to decode the trusted request, said first interface logic to determine that the trusted request is a trusted request from the processor, said first interface logic to further determine that the trusted request targets the token; and
the first interface logic to forward the trusted request to the second interface logic if the trusted request targets the token, said second interface logic to prevent the trusted request from appearing on any bus other than the first bus and the second bus. - View Dependent Claims (12, 13)
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14. A token comprising:
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one or more registers;
an input/output (I/O) bus interface logic to couple the token to a chipset via a bus, said token to receive a trusted request from the chipset, said trusted request to comprise reserved bits that are ignored by one or more devices on the bus. - View Dependent Claims (15, 16)
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17. An apparatus comprising:
a chipset to generate a low pin count (LPC) cycle to a token on a LPC bus, said LPC cycle comprising a start field comprising any one of 0001, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, and 1110. - View Dependent Claims (18, 19, 20, 21)
- 22. A machine readable medium comprising instructions which in response to being executed results in a computing device to issue a request from a processor to a chipset, and to forward the request via a bus to a token, said request encoded to form an encoded request such that other devices on the bus ignore the encoded request.
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26. A chipset comprising:
a dual ported register, said dual ported register to couple a processor to a token, said dual ported register to receive a value for the token from the processor, said processor to write to the token to inform the token to obtain the value from the dual ported register. - View Dependent Claims (27, 28)
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29. A method comprising:
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writing, using a trusted cycle, data to a dual ported register; and
generating a standard Input/Output (I/O) write cycle to a token to inform the token to read the data from the dual ported register. - View Dependent Claims (30)
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31. A method comprising:
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generating a standard Input/Output (I/O) write cycle to a token to inform the token to write data to a dual ported register; and
reading, using a trusted cycle, from the dual ported register the data written by the token.
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32. The method of claim 32 further comprising the token to become a bus master to write data to the dual ported register.
Specification