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Power-on state machine implementation with a counter to control the scan for products with hard-BISR memories

  • US 20030196143A1
  • Filed: 04/11/2002
  • Published: 10/16/2003
  • Est. Priority Date: 04/11/2002
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • a controller circuit configured to present one or more control signals, wherein said control signals are configured to control one or more built-in self-test (BIST) and built-in self-repair (BISR) modes of operation; and

    a BISR assembly circuit comprising one or more memory blocks each comprising a counter configured to generate a clock cycle count value in response to a repair solution, wherein said memory blocks are remapped in response to said count values during one or more of said BISR operations.

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