Power-on state machine implementation with a counter to control the scan for products with hard-BISR memories

• US 20030196143A1
• Filed: 04/11/2002
• Published: 10/16/2003
• Est. Priority Date: 04/11/2002
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Puri, Mukesh K., Agrawal, Ghasi R.
• Granted Patent: US 6,871,297 B2
• Time in Patent Office: Days
• US Class Current: 714/30
• CPC Class Codes: G11C 29/16 using microprogrammed units, e.g. state machines
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/789 using non-volatile cells or latches

Abstract

An apparatus comprising a controller circuit and a BISR assembly circuit. The controller circuit may be configured to present one or more control signals. The control signals may be configured to control one or more built-in self-test (BIST) and built-in self-repair (BISR) modes of operation. The BISR assembly circuit generally comprises one or more memory blocks each comprising a counter configured to generate a clock cycle count value in response to a repair solution during the BIST and BISR operations. The memory blocks may be remapped in response to the count values during one or more of the BISR operations.

Claims

1. An apparatus comprising:

a controller circuit configured to present one or more control signals, wherein said control signals are configured to control one or more built-in self-test (BIST) and built-in self-repair (BISR) modes of operation; and

a BISR assembly circuit comprising one or more memory blocks each comprising a counter configured to generate a clock cycle count value in response to a repair solution, wherein said memory blocks are remapped in response to said count values during one or more of said BISR operations.

2. The apparatus according to claim 1, wherein said count signals are generated in response to one or more memory clock signals that correspond to respective ones of said memory blocks.

3. The apparatus according to claim 1, wherein said apparatus further comprises a state machine configured to present said one or more control signals in response to a power-on signal during one or more of said BISR operations.

4. The apparatus according to claim 3, wherein said state machine is configured to de-assert said one or more control signals in response to the completion of said one or more BISR operations.

5. The apparatus according to claim 2, wherein said memory blocks comprise one or more first registers configured to hold address signals that correspond to one or more faulty memory cells and one or more functional memory cells determined during said BIST and BISR operations.

6. The apparatus according to claim 5, wherein said first registers comprise faulty location analysis and repair execution (FLARE) registers.

7. The apparatus according to claim 5, wherein said apparatus comprises one or more fuse blocks coupled to said first registers and configured to be burned in response to said address signals.

8. The apparatus according to claim 1, wherein said counters are configured to count down said count values and said memory blocks are configured to present one or more BISR control signals in response to completion of said count down.

9. The apparatus according to claim 1, wherein said controller circuit comprises a test access port (TAP) controller.

10. The apparatus according to claim 1, wherein said controller circuit is configured to control one or more normal modes of operation.

11. The apparatus according to claim 5, wherein said BISR assembly circuit comprises a multiplexer coupled to said one or more global registers configured to present said address signals in response to said one or more control signals.

12. The apparatus according to claim 1, wherein said BISR assembly circuit comprises an embedded memory.

13. An apparatus for remapping a memory circuit comprising:

means for presenting one or more control signals, wherein said control signals are configured to control one or more built-in self-test (BIST) and built-in self-repair (BISR) modes of operation of said memory circuit;

means for generating one or more clock cycle count values in response to a repair solution; and

means for controlling said one or more BISR operations in response to said count values.

14. A method for remapping a memory circuit comprising the steps of:

(A) presenting one or more control signals, wherein said control signals are configured to control one or more built-in self-test (BIST) and built-in self-repair (BISR) modes of operation of said memory circuit;

(B) generating one or more clock cycle count values in response to a repair solution; and

(C) controlling said one or more BISR operations in response to said count values.

15. The method according to claim 14, wherein step (A) further comprises the sub-step of:

presenting said one or more control signals in response to a power-on signal during one or more of said BISR operations.

16. The method according to claim 14, wherein step (A) further comprises the sub-step of:

de-asserting said one or more control signals in response to the completion of said one or more BISR operations.

17. The method according to claim 14, wherein step (A) further comprises the sub-steps of:

determining one or more faulty memory cells and one or more functional memory cells during said BIST and BISR operations; and

holding address signals that correspond to said faulty and functional memory cells in one or more first registers.

18. The method according to claim 17, wherein step (A) further comprises the sub-step of:

burning one or more fuses coupled to said first registers in response to said address signals.

19. The method according to claim 14, wherein said memory circuit comprises one or more blocks and each of said blocks is configured to operate in response to one or more memory clock signals.

20. The method according to claim 14, wherein step (C) further comprises the sub-steps of:

counting down said count values; and

presenting one or more of said control signals in response to completion of said counting down.