THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

• US 20030197181A1
• Filed: 10/22/2002
• Published: 10/23/2003
• Est. Priority Date: 04/17/2002
• Status: Active Grant

• Current Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Yun, Hae Jin
• Granted Patent: US 6,642,580 B1
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

A thin film transistor array substrate, and manufacturing methods thereof, having a dual data link structure comprised of a first data link made from a gate metal layer and of a second data link made from a transparent conductive layer. A gate pad made from the gate metal layer electrically connects directly with the first data link, and to the second data link via a data pad protection electrode that passes through contact holes. The data pad protection electrode makes surface connections to the data pad. A data line is electrically connected via a contact electrode to the first data link. The data line and the data pad are formed from different metal layers. The data pad is protected by a gate insulating layer. The contact electrode is extended from the second data link.

Claims

1. A thin film transistor array substrate of a liquid crystal display, comprising:

a pixel electrode;

a thin film transistor connected to the pixel electrode;

a gate line and a data line connected to the thin film transistor;

a gate pad for contacting a gate driver;

a data pad for contacting a data driver;

a gate link connecting the gate pad to the gate line;

a conductive data link connected to the data pad and extending toward the data line; and

a data pad protection electrode electrically connected to the data line and to the conductive data link;

wherein the data pad protection electrode extends over the data link and over the data pad.

2. The thin film transistor array substrate as claimed in claim 1, wherein the data pad, the conductive data link, and the gate line are formed from the same material.

3. The thin film transistor array substrate as claimed in claim 1, further including a gate insulating film over the gate line.

4. The thin film transistor array substrate as claimed in claim 1, wherein the thin film transistor includes a source electrode and a drain electrode, and wherein the data line is formed from the same material as the drain electrode.

5. The thin film transistor array substrate as claimed in claim 1, wherein the data line is comprised of molybdenum.

6. The thin film transistor array substrate as claimed in claim 1, wherein the data pad protection electrode is formed from the same material as the pixel electrode.

7. The thin film transistor array substrate as claimed in claim 6, wherein the data pad protection electrode is transparent.

8. The thin film transistor array substrate as claimed in claim 7, wherein the data pad protection electrode is comprised of material selected from the group consisting of ITO, TO, IZO, and of combinations thereof.

9. The thin film transistor array substrate as claimed in claim 3, wherein said data pad protection electrode electrically contacts to the data pad via a data contact hole through the gate insulating film.

10. The thin film transistor array substrate as claimed in claim 1, further including a protective layer over the gate insulating film on the data pad and between the conductive data link and the data pad protection electrode.

11. The thin film transistor array substrate as claimed in claim 10, wherein said data pad protection electrode electrically contacts the data pad via a data contact hole through the gate insulating film and through the protective layer.

12. The thin film transistor array substrate as claimed in claim 10, wherein said data pad protection electrode electrically contacts the data line via a data line hole through the protective layer and through the data line, wherein the data pad protection electrode electrically contacts to the data line via the data line hole.

13. The thin film transistor array substrate as claimed in claim 12, wherein the data line is comprised of molybdenum.

14. The thin film transistor array substrate as claimed in claim 1, wherein the conductive data link includes a first data link that extends from the data pad toward the data line and a second data link over the first data link.

15. The thin film transistor array substrate as claimed in claim 14, wherein the first data link is comprised of the same material as the data pad, and wherein the second data link is comprised of the same material as the pixel electrode.

16. The thin film transistor array substrate as claimed in claim 15, wherein the second data link is part of the data pad protection electrode.

17. The thin film transistor array substrate as claimed in claim 15, wherein the conductive data link and the data line electrically connect using a contact electrode that is electrically connected to the data pad protection electrode.

18. The thin film transistor array substrate as claimed in claim 17, wherein the contact electrode electrically connects to data line though holes in a protective layer.

19. The thin film transistor array substrate as claimed in claim 1, wherein the data pad protection electrode is in surface contact with the data pad.

20. A method of manufacturing a thin film transistor array substrate of a liquid crystal display, comprising the steps of:

(A) forming on a substrate a gate line and a crossing data line that are separated by a gate insulating film, a thin film transistor adjacent the crossing, a gate link and a gate pad that extends from the gate line, a data pad under the gate insulating film, and a data link that extends from the data pad toward the data line;

(B) forming a protective film over the entire surface of the substrate after completing step (a);

(C) defining a plurality of first contact holes and second contact holes through the protective film and through the gate insulating film;

wherein the first contact holes expose the data link, and wherein the second contact holes expose the data pad;

(D) defining a plurality of third contact holes through the protective film, wherein the third contact holes expose the data line;

(E) forming a pixel electrode that is electrically connected to the thin film transistor and a data pad protection electrode that is connected to the data link via the first contact holes, to the data pad via the second contact holes, and to the data line via the third contact holes.

21. The method as claimed in claim 20, wherein step (A) includes:

depositing a gate metal material onto the substrate and then patterning the gate metal material to form a gate electrode of the thin film transistor, the gate line, the gate pad, the data pad and the data link;

forming the gate insulating film;

depositing a semiconductor material on the gate insulating film and then patterning the semiconductor material to form an active layer and an ohmic contact layer of the thin film transistor; and

depositing a drain metal material over the semiconductor material and the gate insulating film, and then patterning the drain metal material to form the data line and source and drain electrodes of the thin film transistor.

22. The method as claimed in claim 20, wherein the step of forming the data pad protection electrode includes forming the data pad protection electrode from the same material as the pixel electrode.

23. The method as claimed in claim 22, wherein the step of forming the data pad protection electrode includes forming the data pad protection electrode from a transparent material.

24. The method as claimed in claim 23, wherein the step of forming the data pad protection electrode includes forming the data pad protection electrode from a material selected from the group consisting of ITO, TO, IZO, and combinations thereof.

25. The method as claimed in claim 20, wherein the step of forming the data line includes forming the data line from molybdenum.

26. The method as claimed in claim 20, wherein the step of forming the third contact holes includes forming the third contact holes through the data line such that the data line is exposed through the sides of the third contact holes, and wherein the step of forming the data pad protection electrode includes forming the data pad protection electrode in electrical contact with the data line along the sides of the third contact holes.