Structure and fabrication method of electrostatic discharge protection circuit

• US 20030197225A1
• Filed: 04/29/2002
• Published: 10/23/2003
• Est. Priority Date: 04/22/2002
• Status: Abandoned Application

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Tang, Tien-Hao, Hsu, Tsun-Lai, Chen, Shiao-Shien, Tseng, Hua-Chou
• Application Number:
  US10/134,835
• Publication Number:
  US 20030197225A1
• Time in Patent Office: Days
• US Class Current: 257/355
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Abstract

A structure of an electrostatic discharge protection circuit, in which a buried layer is formed in the substrate of the electrostatic discharge protection circuit, and a sinker layer electrically connected to the buried layer and a drain is also formed therein. Thereby, when the electrostatic discharge protection circuit is activated, the current flows from a source through the buried layer and the sinker layer to the drain. The current flow path is remote from the gate dielectric layer to avoid damaging the gate dielectric by a large current, so as to improve the dielectric strength of the electrostatic discharge protection circuit.

Claims

1. An electrostatic discharge protection circuit, comprising:

a substrate;

a well, formed in the substrate and doped with a first conductive type;

a transistor, formed in the well and having a gate, a drain and a source;

a substrate-connecting region, formed in the well at a periphery of the transistor, wherein the substrate-connecting region is doped with the first conductive type;

a first isolation layer, formed in the well to isolate the substrate-connecting region from the transistor;

a buried layer, formed at a junction between the well and the substrate under the transistor, wherein the buried layer is doped with a second conductive type; and

a sinker layer, formed between the buried layer and the drain and electrically connected to the buried layer and the drain, wherein the sinker layer is doped with the second conductive type.

2. The electrostatic discharge protection circuit according to claim 1, further comprising a guard ring formed in the substrate, wherein the guard ring is isolated from the substrate-connecting region by a second isolation layer.

3. The electrostatic discharge protection circuit according to claim 1, wherein the guard ring is doped with the second conductive type.

4. The electrostatic discharge protection circuit according to claim 1, wherein the sinker layer has a width narrower than that of the drain.

5. The electrostatic discharge protection circuit according to claim 1, wherein the buried layer has a width extending from the source to the drain of the transistor.

6. The electrostatic discharge protection circuit according to claim 1, wherein the first conductive type includes P type, and the second conductive type includes N type.

7. The electrostatic discharge protection circuit according to claim 1, wherein the first conductive type includes N type, and the second conductive type includes P type.

8. A method for fabricating an electrostatic discharge protection circuit, comprising:

providing a substrate;

forming a well in the substrate, wherein the well is doped with a first conductive type;

forming a buried layer at a lateral junction between the well and the substrate, wherein the buried layer is doped with a second conductive type;

forming a sinker layer doped with the second conductive type in the well, wherein the sinker layer is electrically connected to the buried layer;

forming a gate in the well;

forming a source and a drain in the well at two sides of the gate, wherein the drain is electrically connected to the sinker layer; and

forming a substrate-connecting region in the well.

9. The method according to claim 8, wherein the step for forming the buried layer includes ion implantation.

10. The method according to claim 8, wherein the step of forming the buried layer includes forming the buried layer with a width extending from the source to the drain under the transistor.

11. The method according to claim 8, wherein the step of forming the sinker layer includes ion implantation.

12. The method according to claim 8, wherein the steps for forming the sinker layer include forming the sinker layer with a width narrower than that of the drain.

13. The method according to claim 8, wherein the first conductive type includes P type and the second conductive type includes N type.

14. The method according to claim 8, wherein the first conductive type includes N type and the second conductive type includes P type.

15. A method of fabricating a semiconductor device, which comprises a bipolar transistor, a CMOS and an electrostatic discharge protection circuit, the method comprising

providing a substrate, which comprises an electrostatic discharge protection circuit region, a bipolar transistor region and a CMOS transistor region, wherein a first P well is formed in the electrostatic discharge protection circuit, a second P well is formed in the CMOS transistor region, and an N well is formed in the bipolar transistor region;

simultaneously forming a first buried layer at a lateral junction between the first P well and the substrate, and a second buried layer at a lateral junction between the N well and the substrate;

simultaneously forming a first sinker layer in the first P well and a second sinker layer in the N well, wherein the first sinker layer is electrically connected to the first buried layer, and the second sinker layer is electrically connected to the second buried layer;

forming a first NMOS gate on the first P well, a second NMOS gate on the second P well, and a conductive layer on the N well;

forming a first NMOS source and a first NMOS drain in the first P well at two sides of the first NMOS gate and a second NMOS source and a second NMOS drain in the second P well at two sides of the second NMOS gate simultaneously;

forming a first P+ substrate-connecting region in the first P well and a second P+ substrate-connecting region in the second P well simultaneously; and

forming a bipolar transistor on the conductive layer.

16. The method according to claim 15, wherein the step of forming the first and second buried layers includes forming the first and second buried layers with a width extending from the first NMOS and the second NMOS sources to the first NMOS and the second NMOS drains under the first and the second transistors, respectively.

17. The method according to claim 15, wherein the step of forming the first and the second sinker layers includes forming the first and the second sinker layers with a width narrower than those of the first and the second NMOS drains, respectively.

18. The method according to claim 15, wherein the first and the second buried layers are formed in the same process.

19. The method according to claim 15, wherein the first and the second sinker layers are formed in the same process.