Clock distribution networks and conductive lines in semiconductor integrated circuits

• US 20030197239A1
• Filed: 02/26/2003
• Published: 10/23/2003
• Est. Priority Date: 04/18/2002
• Status: Abandoned Application

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Siniaguine, Oleg
• Application Number:
  US10/375,218
• Publication Number:
  US 20030197239A1
• Time in Patent Office: Days
• US Class Current: 257/459
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A clock distribution network (110) is formed on a semiconductor interposer (320) which is a semiconductor integrated circuit. An input terminal (120) of the clock distribution network is formed on one side of the interposer, and output terminals (130) of the clock distribution network are formed on the opposite side of the interposer. The interposer has a through hole (360), and the clock distribution network includes a conductive feature going through the through hole. The side of the interposer which has the output terminals (130) is bonded to a second integrated circuit (310) containing circuitry clocked by the clock distribution network. The other side of the interposer is bonded to a third integrated circuit or a wiring substrate (330). The interposer contains a ground structure, or ground structures (390, 510), that shield circuitry from the clock distribution network. Conductive lines (150) in an integrated circuit are formed in trenches (610) in a semiconductor substrate.

Claims

1. An apparatus comprising a first semiconductor integrated circuit comprising:

a first surface and a second surface that are opposite to each other; and

a clock distribution network having an input terminal which is a contact pad at the second surface and having a plurality of output terminals which are contact pads at the first surface.

2. The apparatus of claim 1 wherein the first semiconductor integrated circuit comprises a first semiconductor substrate which has a through hole passing between the first and second surfaces, and the clock distribution network comprises a conductive feature going through the through hole.

3. The apparatus of claim 2 wherein the conductive feature forms an angle of at least 30°

with at least one of the first and second surfaces or with at least one of the first semiconductor substrate'"'"'s surfaces adjacent to the first and second surfaces.

4. The apparatus of claim 2 wherein:

the first semiconductor substrate further comprises one or more additional through holes passing between the first and second surfaces; and

the first semiconductor integrated circuit further comprises;

one or more additional contact pads at the second surface at each of the additional through holes;

an additional conductive feature in each of the through holes, the conductive feature providing at least a portion of a path for a signal and/or a power voltage and/or a ground voltage between the corresponding additional contact pad and a circuit element at the first surface.

5. The apparatus of claim 4 wherein for at least one conductive feature, the corresponding circuit element at the first surface is a contact pad.

6. The apparatus of claim 5 wherein for said at least one conductive feature, the corresponding circuit element at the first surface is located above the respective through hole, and the entire electrical path connecting the circuit element at the first surface to the respective additional contact pad at the second surface forms an angle of at least 30°

with at least one of the first and second surfaces or with at least one of the semiconductor substrate'"'"'s surfaces adjacent to the first and second surfaces.

7. The apparatus of claim 4 wherein the clock distribution network comprises a plurality of conductive lines, and the conductive features in all of said through holes form angles of at least 30°

with at least one of the first and second surfaces or with at least one of the semiconductor substrate'"'"'s surfaces adjacent to the first and second surfaces.

8. The apparatus of claim 1 wherein the first integrated circuit comprises:

a first semiconductor substrate; and

a conductive structure to be held at a constant voltage, wherein at least a portion of the clock distribution network is located between the conductive structure and the first semiconductor substrate.

9. The apparatus of claim 8 wherein the conductive structure comprises a conductive plane or a conductive grid.

10. The apparatus of claim 1 wherein the first integrated circuit comprises:

a first semiconductor substrate; and

a conductive structure to be held at a constant voltage, wherein at least a portion of the clock distribution network is separated from the first semiconductor substrate by the conductive structure.

11. The apparatus of claim 10 wherein the conductive structure comprises a conductive plane or a conductive grid.

12. The apparatus of claim 1 further comprising a second semiconductor integrated circuit comprising a plurality of contact pads positioned at a first surface of the second semiconductor integrated circuit and bonded to the contact pads that are the output terminals of the clock distribution network.

13. The apparatus of claim 12 wherein the first integrated circuit comprises a first conductive structure between at least a portion of the clock distribution network and the second integrated circuit, and the first conductive structure is held at a constant voltage during operation of the apparatus.

14. The apparatus of claim 13 wherein the first conductive structure comprises a conductive plane or a conductive grid.

15. The apparatus of claim 13 further comprising a third circuit which is a wiring substrate and/or a semiconductor integrated circuit, wherein the third circuit comprises one or more contact pads bonded to one or more contact pads of the first integrated circuit which are located at the second surface of the first integrated circuit;

wherein the first integrated circuit comprises a second conductive structure to be held at a constant voltage, wherein the second conductive structure is located between at least a portion of the clock distribution network and the third circuit.

16. The apparatus of claim 13 wherein the second conductive structure comprises a conductive plane or a conductive grid.

17. The apparatus of claim 12 wherein the clock distribution network is a part of a larger clock distribution network, and the larger clock distribution network has another part located in the second integrated circuit.

18. The apparatus of claim 1 wherein the first integrated circuit comprises a first semiconductor substrate which has a trench therein, and the clock distribution network comprises a conductive line formed in the trench and interconnecting two nodes of the clock distribution network.

19. The apparatus of claim 18 wherein the first integrated circuit further comprises a dielectric insulating the conductive line from the first semiconductor substrate.

20. The apparatus of claim 18 wherein the first integrated circuit further comprises:

a first conductive layer located between the conductive line and a surface of the trench, wherein the first conductive layer is held at a constant voltage during operation of the apparatus;

a first dielectric insulating the first conductive layer from the conductive line; and

a second dielectric insulating the first conductive layer from the first substrate.

21. The apparatus of claim 20 wherein the first integrated circuit further comprises:

a third dielectric overlying the conductive line; and

a second conductive layer overlying the conductive line and insulated from the conductive line by the third dielectric, wherein the second conductive layer physically contacts the first conductive layer so as to be at the same voltage as the first conductive layer.

22. The apparatus of claim 21 wherein the second conductive layer extends over the entire conductive line.

23. An integrated circuit comprising:

a semiconductor substrate having a trench therein; and

a conductive line formed in the trench and interconnecting two laterally spaced nodes of the integrated circuit.

24. The integrated circuit of claim 23 wherein the two nodes are located at two different ends of the conductive line.

25. The integrated circuit of claim 23 wherein the trench is part of a trench network having conductive lines formed therein.

26. The integrated circuit of claim 25 wherein the trench network comprises a tree network of trenches, and the conductive lines comprise a tree network of conductive lines.

27. The integrated circuit of claim 25 wherein the trench network comprises a grid of trenches, and the conductive lines comprise a grid network of conductive lines.

28. The integrated circuit of claim 23 wherein the conductive line is part of a clock distribution network.

29. The integrated circuit of claim 23 further comprising a dielectric insulating the conductive line from the substrate.

30. The integrated circuit of claim 23 further comprising:

a first conductive layer located between the conductive line and surfaces of the trench, wherein the first conductive layer is held at a constant voltage during operation of the integrated circuit;

a first dielectric insulating the first conductive layer from the conductive line; and

a second dielectric insulating the first conductive layer from the substrate.

31. The integrated circuit of claim 30 further comprising:

a third dielectric overlying the conductive line; and

a second conductive layer overlying the conductive line and insulated from the conductive line by the third dielectric, wherein the second conductive layer physically contacts the first conductive layer so as to be at the same voltage as the first conductive layer.

32. The integrated circuit of claim 31 wherein the second conductive layer extends over the entire conductive line.

33. A manufacturing method comprising manufacturing a first semiconductor integrated circuit comprising a first surface and a second surface that are opposite to each other, wherein the first semiconductor integrated circuit comprises a clock distribution network having an input contact pad at the second surface and having a plurality of output contact pads at the first surface.

34. A manufacturing method comprising bonding of a first semiconductor integrated circuit to a second semiconductor integrated circuit;

wherein the first semiconductor integrated circuit comprises;

a first surface and a second surface that are opposite to each other; and

a clock distribution network having an input contact pad at the second surface and having a plurality of output contact pads at the first surface;

wherein the second semiconductor integrated circuit comprises a plurality of contact pads positioned at a first surface of the second semiconductor integrated circuit; and

the bonding operation comprises bonding the contact pads of the second semiconductor integrated circuit to respective output contact pads of the clock distribution network.

35. A method comprising:

providing a clock signal to an input contact pad of a clock distribution network formed in a first semiconductor integrated circuit;

the clock distribution network coupling the clock signal to output contact pads, wherein the output contact pads are located at a first surface of the first integrated circuit and the input contact pad is located at a second surface of the first integrated circuit, the second surface being opposite to the first surface;

wherein the output contact pads are bonded to contact pads of a second semiconductor integrated circuit.

36. A manufacturing method comprising:

forming a trench in a semiconductor substrate; and

forming a conductive line in the trench to interconnect two laterally spaced nodes of circuitry.

37. The method of claim 36 wherein the two nodes are located at two different ends of the conductive line.

38. The method of claim 36 wherein the trench is part of a trench network having conductive lines formed therein.

39. The method of claim 38 wherein the trench network comprises a tree network of trenches, and the conductive lines comprise a tree network of conductive lines.

40. The method of claim 38 wherein the trench network comprises a grid of trenches, and the conductive lines comprise a grid network of conductive lines.

41. The method of claim 36 wherein the conductive line is part of a clock distribution network.

42. The method of claim 36 further comprising forming dielectric insulating the conductive line from the substrate.

43. The method of claim 36 further comprising:

forming a first conductive layer located between the conductive line and surfaces of the trench, wherein the first conductive layer is held at a constant voltage during operation of the circuitry;

forming a first dielectric insulating the first conductive layer from the conductive line; and

before forming the conductive layer, forming a second dielectric insulating the first conductive layer from the substrate.

44. The method of claim 43 further comprising:

forming a third dielectric overlying the conductive line; and

forming a second conductive layer overlying the conductive line and insulated from the conductive line by the third dielectric, wherein the second conductive layer physically contacts the first conductive layer so as to be at the same voltage as the first conductive layer.

45. The method of claim 44 wherein the second conductive layer extends over the entire conductive line.