Clock distribution networks and conductive lines in semiconductor integrated circuits
First Claim
1. An apparatus comprising a first semiconductor integrated circuit comprising:
- a first surface and a second surface that are opposite to each other; and
a clock distribution network having an input terminal which is a contact pad at the second surface and having a plurality of output terminals which are contact pads at the first surface.
1 Assignment
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Accused Products
Abstract
A clock distribution network (110) is formed on a semiconductor interposer (320) which is a semiconductor integrated circuit. An input terminal (120) of the clock distribution network is formed on one side of the interposer, and output terminals (130) of the clock distribution network are formed on the opposite side of the interposer. The interposer has a through hole (360), and the clock distribution network includes a conductive feature going through the through hole. The side of the interposer which has the output terminals (130) is bonded to a second integrated circuit (310) containing circuitry clocked by the clock distribution network. The other side of the interposer is bonded to a third integrated circuit or a wiring substrate (330). The interposer contains a ground structure, or ground structures (390, 510), that shield circuitry from the clock distribution network. Conductive lines (150) in an integrated circuit are formed in trenches (610) in a semiconductor substrate.
23 Citations
45 Claims
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1. An apparatus comprising a first semiconductor integrated circuit comprising:
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a first surface and a second surface that are opposite to each other; and
a clock distribution network having an input terminal which is a contact pad at the second surface and having a plurality of output terminals which are contact pads at the first surface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. An integrated circuit comprising:
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a semiconductor substrate having a trench therein; and
a conductive line formed in the trench and interconnecting two laterally spaced nodes of the integrated circuit. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. A manufacturing method comprising manufacturing a first semiconductor integrated circuit comprising a first surface and a second surface that are opposite to each other, wherein the first semiconductor integrated circuit comprises a clock distribution network having an input contact pad at the second surface and having a plurality of output contact pads at the first surface.
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34. A manufacturing method comprising bonding of a first semiconductor integrated circuit to a second semiconductor integrated circuit;
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wherein the first semiconductor integrated circuit comprises;
a first surface and a second surface that are opposite to each other; and
a clock distribution network having an input contact pad at the second surface and having a plurality of output contact pads at the first surface;
wherein the second semiconductor integrated circuit comprises a plurality of contact pads positioned at a first surface of the second semiconductor integrated circuit; and
the bonding operation comprises bonding the contact pads of the second semiconductor integrated circuit to respective output contact pads of the clock distribution network.
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35. A method comprising:
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providing a clock signal to an input contact pad of a clock distribution network formed in a first semiconductor integrated circuit;
the clock distribution network coupling the clock signal to output contact pads, wherein the output contact pads are located at a first surface of the first integrated circuit and the input contact pad is located at a second surface of the first integrated circuit, the second surface being opposite to the first surface;
wherein the output contact pads are bonded to contact pads of a second semiconductor integrated circuit.
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36. A manufacturing method comprising:
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forming a trench in a semiconductor substrate; and
forming a conductive line in the trench to interconnect two laterally spaced nodes of circuitry. - View Dependent Claims (37, 38, 39, 40, 41, 42, 43, 44, 45)
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Specification