Lateral type power MOS transistor and fabrication method thereof

• US 20030197240A1
• Filed: 03/21/2003
• Published: 10/23/2003
• Est. Priority Date: 03/28/2002
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Compound Semiconductor Devices, Ltd. (NEC Corporation)
• Inventors: Ishihara, Sho
• Granted Patent: US 6,812,522 B2
• Time in Patent Office: Days
• US Class Current: 257/500
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors

Abstract

A groove 34 having a generally U-shape cross section is formed in an N⁻ type semiconductor layer 33 of an SOI substrate 30. A P⁻ type well region 36 reaching a buried silicon oxide film 32 is formed in a surface layer on one side of the groove 34 and an N type well region 35 having substantially the same depth as that of the groove 34 is formed in the surface layer on the other side of the groove 34. A PN junction formed by the P⁻ type well region 36 and the semiconductor layer 33 is formed in substantially coplanar with the side wall of the groove 34 on the side of the P⁻ type well region 36. A P type base region 37 having substantially the same depth as that of the groove 34 and adjacent to the side wall of the groove 34 is formed in a surface layer of the P⁻ type well region 36. An N⁺ type drain region 38 is formed in a surface layer of the N type well region 35 and an N⁺ type source region 39 adjacent to the side wall of the groove 34 is formed in a surface layer of the P type base region 37.

Claims

1. A lateral type power MOS transistor comprising:

a support substrate;

a buried insulating film formed on said support substrate;

a semiconductor layer of a first conductivity type formed on said buried insulating film;

a groove formed in said semiconductor layer of said first conductivity type;

a base region of a second conductivity type formed from a surface of said semiconductor layer of said first conductivity type adjacent to one of side walls of said groove to a depth substantially equal to a depth of said groove;

a high impurity density source region of said first conductivity type formed from a surface of said base region and extending in a depth direction of said base region adjacent to one of said side walls of said groove, an impurity density of said high impurity density source region being higher than that of said semiconductor layer;

a low impurity density region of the other conductivity type formed between said base region and said buried insulating film, an impurity density of said low impurity density region being lower than that of said base region;

a drain region of said first conductivity type formed from a surface of said semiconductor layer on the other side wall of said groove and extending in a depth direction thereof, an impurity density of said drain region being higher than that of said semiconductor layer;

a gate insulating film formed in said groove;

a gate electrode formed on said gate insulating film within said groove and opposing to said base region; and

a PN junction formed by said low impurity density region and said semiconductor layer, one end of said PN junction being in contact with said groove and the other end of said PN junction being in contact with said buried insulating film.

2. A lateral type power MOS transistor as claimed in claim 1, wherein an impurity density of a portion of said semiconductor layer, attributing to the formation of said PN junction, is lower than that of a region of said semiconductor layer existing adjacent to said the other side wall of said groove below-said drain region to form a low impurity density region of said first conductivity type.

3. A lateral type power MOS transistor as claimed in claim 2, wherein thickness of said low impurity density region of said first conductivity type is smaller than the depth of said groove.

4. A lateral type power MOS transistor as claimed in claim 2, wherein said low impurity density region of said first conductivity type and said low impurity density region of said second conductivity type have the same thickness and are positioned below a bottom of said groove.

5. A lateral type power MOS transistor as claimed in claim 1, wherein the depth of said groove is larger than a width of said groove.

6. A lateral type power MOS transistor as claimed in claim 1, wherein a size of said gate electrode in the depth direction of said groove is smaller than the depth of said groove and the whole of said gate electrode is positioned within said groove.

7. A lateral type power MOS transistor as claimed in claim 1, wherein said support substrate is an N type silicon substrate, said insulating film formed on said support substrate is a buried silicon oxide film, said semiconductor layer of said first conductivity type formed on said insulating film is an N⁻

type silicon layer, said base region of said second conductivity type is a P type silicon region, said low impurity density region of said second conductivity type is a P⁻

type silicon region, said high impurity density source region of said first conductivity type and said drain region of said first conductivity type are N⁺ type silicon regions, impurity densities of said low impurity density region of said second conductivity type formed between said base region and said insulating film and said low impurity density region of said second conductivity type are lower than that of said base region and said gate insulating film is a silicon oxide film.

8. A fabrication method for fabricating a lateral type power MOS transistor, comprising the steps of:

preparing an SOI having an electrically conductive support substrate, an insulating film formed thereon and a semiconductor layer of one conductivity type formed on said insulating film;

forming, in said semiconductor layer of said first conductivity type, a low impurity density well region of said second conductivity type reaching said insulating film;

forming a groove having a depth smaller than a distance measured from an upper surface of said semiconductor layer to said insulating film in said semiconductor layer of said first conductivity type adjacent to a side wall of said well region of said second conductivity type;

forming a gate insulating film and a gate electrode in said groove, sequentially;

forming, in a surface of said well region of said second conductivity type, a base region of said second conductivity type adjacent to a side wall of said groove, a depth of said base region being substantially the same as that of said groove; and

forming, in a surface of said base region, a high impurity density source region of said first conductivity type adjacent to a side wall on one side of said groove and, in said semiconductor layer of said first conductivity type, a high impurity density drain region of said first conductivity type on the other side of said groove.