Semiconductor package

• US 20030197284A1
• Filed: 02/11/2003
• Published: 10/23/2003
• Est. Priority Date: 02/21/2002
• Status: Active Grant

• Current Assignee: Utac Headquarters Pte. Ltd (UTAC Holdings Ltd.)
• Original Assignee: United Test and Assembly Center Limited (UTAC Holdings Ltd.)
• Inventors: Chin, Fong Kok, Chuan, Koh Yong, Khiang, Wang Chuen
• Granted Patent: US 8,288,862 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 2225/06579 TAB carriers; beam leads
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor package, containing two or more stacked IC devices attached to a substrate. Each of the IC devices has a plurality of electrical contact regions which are connected to the substrate by means of electrical connections.

Claims

1. A semiconductor package comprising:

a first IC device;

a second IC device; and

a substrate;

wherein the first IC device is attached to the substrate and the second IC device is attached to the first IC device;

the semiconductor package further comprising a first electrical connection between the first IC device and the substrate and a second electrical connection between the second IC device and the substrate.

2. A semiconductor package according to claim 1, wherein the substrate is attached to a first major face of the first IC device and the second IC device is attached to a second major face of the first IC device.

3. A semiconductor package according to claim 1 or 2, further comprising:

an opening, through the substrate from a first side to which the first IC device is attached, to a second, opposite, side of the substrate;

an electrical contact region on the first IC device; and

wherein said first electrical connection passes through said opening and connects said electrical contact region on the first IC device to the second side of the substrate.

4. A semiconductor package according to claim 3, wherein said electrical contact region on the first IC device is part of a first row of electrical contact regions on the first IC device;

and the semiconductor package further comprises;

a second opening through the substrate from the first side to the second side;

a second row of electrical contact regions on the first IC device; and

a third electrical connection, passing through said second opening and connecting an electrical contact region in said second row of electrical contact regions on the first IC device to the second side of the substrate.

5. A semiconductor package according to claim 4, wherein said first and second rows of electrical contact regions on the first IC device are located on mutually opposite edges of a first side of the first IC device, to which the substrate is attached.

6. A semiconductor package according to claim 3 or 4, wherein the first electrical contact region on the first IC device is part of a row of electrical contact regions on the first IC device, said row located substantially centrally on a first side of the first IC device, to which the substrate is attached.

7. A semiconductor package according to any preceding claim, further comprising an electrical contact region on the second IC device and said second electrical connection connects the electrical region on the second IC device to the substrate.

8. A semiconductor package according to claim 7, wherein said electrical contact region on the second IC device is part of a first row of electrical contact regions on the second IC device;

and the semiconductor package further comprises a second row of electrical contact regions on the second IC device and a fourth electrical connection connecting an electrical contact region in the second row of electrical contact regions on the second IC device to the substrate.

9. A semiconductor package according to claim 8, wherein said first and second rows of electrical contact regions on the second IC device are located on mutually opposite edges of a first side of the second IC device, which is on the other side of the second IC device to a second side, to which the first IC device is attached.

10. A semiconductor package according to claim 6 or 7, wherein said first electrical contact region on the second IC device is part of a row of electrical contact regions on the second IC device, said row located substantially centrally on a first side of the second IC device, which is on the other side of the second IC device to a second side, to which the first IC device is attached.

11. A semiconductor package according to any preceding claim, further comprising at least a third IC device, the third IC device attached to the second IC device by means of a spacer;

and one or more electrical connections, connecting an electrical contact region on each of the IC devices to the substrate.

12. A semiconductor package according to any preceding claim, further comprising an electrical contact distribution means, attached to an IC device in the semiconductor package;

wherein an electrical connection is connected to its associated electrical contact region via the electrical contact distribution means.

13. A semiconductor package according to claim 12, wherein the electrical contact distribution means is comprised of:

a wafer distribution layer;

a substrate interposer;

a dielectric interposer;

a metallic interposer;

or

any combination of these.

14. A semiconductor package according to any preceding claim, wherein the first IC device performs a different function to the second IC device.