Multiple chips bonded to packaging structure with low noise and multiple selectable functions

• US 20030197287A1
• Filed: 05/13/2003
• Published: 10/23/2003
• Est. Priority Date: 05/19/2000
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megic Corporation (Chipbond Technology Corporation)
• Inventors: Peng, Bryan, Lin, Mou-Shiung
• Granted Patent: US 6,768,208 B2
• Time in Patent Office: Days
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01055 Cesium [Cs]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15151 the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15331 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/09309 : Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/10674 : Flip chip

Abstract

A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.

Claims

1. A method of forming a chip package for a semiconductor chip including the steps as follows:

forming a printed circuit board having a top surface and a bottom surface including a power structure and a ground structure which are selected from;

a) a power bus and a ground bus, and

b) a power plane and a ground plane located within the printed circuit board,

forming solder connections between the printed circuit board and a chip overlying the printed circuit board in a flip chip connection,

providing a bypass capacitor with a first terminal and a second terminal, and

connecting the first terminal of the bypass capacitor to the power structure and connecting the second terminal of the bypass capacitor to the ground structure.

3. The method of claim 1 including:

juxtaposing the capacitor with the chip, and

connecting the first terminal to the power plane and the second terminal is connecting to the ground plane.

4. The method of claim 1 including:

locating the capacitor on the opposite surface of the printed circuit board from the chip, and

connecting the first terminal to the power plane and connecting the second terminal to the ground plane.

5. The method of claim 1 including:

locating the capacitor on the opposite surface of the printed circuit board from the chip,

connecting the first terminal to the power plane and connecting the second terminal to the ground plane, and

connecting big solder balls to the opposite surface of the printed circuit board for interconnection thereof with another element.

2. The method of claim I including:

juxtaposing the capacitor and the power bus and the ground bus with the chip, and

connecting the first terminal to the power bus and connecting the second terminal to the ground bus.

6. A package for semiconductor chips including:

a printed circuit board having a top surface and a bottom surface including a power structure and a ground structure which are selected from;

a) a power bus and a ground bus, and

b) a power plane and a ground plane located within the printed circuit board,

solder connections between the printed circuit board and a chip overlying the printed circuit board in a flip chip connection,

a bypass capacitor with a first terminal and a second terminal, and

the first terminal of the bypass capacitor being connected to the power structure and the second terminal being connected to the ground structure.

7. The package of claim 6 wherein:

the capacitor and the power bus and the ground bus are juxtaposed with the chip, and

the first terminal is connected to the power bus and the second terminal is connected to the ground bus.

9. The package of claim 6 wherein:

the capacitor is located on the opposite surface of the printed circuit board from the chip, and

the first terminal is connected to the power plane and the second terminal is connected to the ground plane.

10. The package of claim 6 wherein:

the capacitor is located on the opposite surface of the printed circuit board from the chip,

the first terminal is connected to the power plane and the second terminal is connected to the ground plane, and

big solder balls are connected to the opposite surface of the printed circuit board for interconnection thereof with another element.

8. The package of claim G wherein:

the capacitor is juxtaposed with the chip, and

the first terminal is connected to the power plane and the second terminal is connected to the ground plane.

11. A method of forming a chip package for a semiconductor chip including the steps as follows:

forming a first printed circuit board having a top surface and a bottom surface including a power plane and a ground plane located within the first printed circuit board,

forming a second printed circuit board having a top surface and a bottom surface,

bonding a first chip to the top surface of the first printed circuit board and bonding a second chip to the bottom surface of the first printed circuit board in a flip chip connection,

bonding a third chip to the bottom surface of the second printed circuit board in a flip chip connection, and

bonding the chips to the printed circuit boards by means selected from the following;

a) solder balls, and

b) gold bumps.

12. The method of claim 11 including:

providing a bypass capacitor with a first terminal and a second terminal, and

connecting the first terminal of the bypass capacitor to the power plane and connecting the second terminal of the bypass capacitor to the ground plane.

13. The method of claim 11 including:

bonding a fourth chip to the top surface of the second printed circuit board in a flip chip connection,

interconnecting the bottom surface of the first printed circuit board and the top surface of the second printed circuit board with big solder balls.

14. The method of claim 13 including:

bonding the chips to the printed circuit boards by means selected from the following;

a) solder balls, and

b) gold bumps.

15. The method of claim 11 including:

bonding a fourth chip to the top surface of the second printed circuit board,

providing a bypass capacitor with a first terminal and a second terminal, and

connecting the first terminal of the bypass capacitor to the power plane and connecting the second terminal of the bypass capacitor to the ground plane.

20. The package of claim 15 including:

a fourth chip bonded to the top surface of the second printed circuit board,

a bypass capacitor with a first terminal and a second terminal, and

the first terminal of the bypass capacitor connected to the power plane and the second terminal of the bypass capacitor connected to the ground plane.

16. A chip package for a semiconductor chip including:

a first printed circuit board having a top surface and a bottom surface including a power plane and a ground plane located within the first printed circuit board,

a second printed circuit board having a top surface and a bottom surface,

a first chip bonded to the top surface of the first printed circuit board and a second chip bonded to the bottom surface of the first printed circuit board in a flip chip connection,

a third chip bonded to the bottom surface of the second printed circuit board in a flip chip connection,

a bypass capacitor with a first terminal and a second terminal,

the first terminal of the bypass capacitor connected to the power plane and the second terminal of the bypass capacitor connected to the ground plane, and

the bottom surface of the first printed circuit board interconnected to the top surface of the second printed circuit board with a solder ball.

17. The package of claim 16 including:

a bypass capacitor with a first terminal and a second terminal, and

the first terminal of the bypass capacitor connected to the power plane and the second terminal of the bypass capacitor connected to the ground plane.

18. The package of claim 16 including:

a fourth chip bonded to the top surface of the second printed circuit board in a flip chip connection,

the bottom surface of the first printed circuit board interconnected to the top surface of the second printed circuit board with big solder balls.

19. The package of claim 18 including:

the chips bonded to the printed circuit boards by means selected from the following;

a) solder balls, and

b) gold bumps.

21. A method of forming a chip package for semiconductor chips including the steps as follows:

forming a printed circuit board with a window therethrough having a length and a width and a top surface and a bottom surface,

semiconductor chips including a primary chip and a secondary chip,

forming bonded connections between the top surface of the printed circuit board and the primary chip, with the primary chip overlying the window and which extends transversely across the width of the window,

locating the secondary chip suspended within the window and forming bonded connections between the secondary semiconductor chip and the primary chip in a chip-on-chip connection.

22. The method of claim 21 including:

the window having a width less than the length,

the primary chip and the secondary chip having substantially equal chip lengths and substantially equal chip widths.

23. The method of claim 21 including:

forming the bonded connections of the chips to the printed circuit boards by means selected from the following;

a) solder balls, and

b) gold bumps.

24. The method of claim 21 including:

forming the bonded connections of the chips to the printed circuit board by means selected from the following;

a) solder balls, and

b) gold bumps, and

forming big solder balls on the top surface of the printed circuit board,

the window having a width less than the length,

the primary chip and the secondary chip having substantially equal chip lengths and substantially equal chip widths.

31. The method of claim 21 including:

forming the bonded connections between the top surface of the substrate and the primary chip aside from the secondary chip with big solder balls,

the substrate comprising a ball grid array substrate, and

the bonded connections of the chips to the substrate being provided by means selected from the following;

a) solder balls, and

b) gold bumps.

33. The package of claim 31 including:

the substrate comprising a ball grid array substrate, and

the bonded connections of the chips to the substrate being provided by means selected from the following;

a) solder balls, and

b) gold bumps.

34. The package of claim 21 including:

bonded connections between the top surface of the substrate and the primary chip aside from the secondary chip with big solder balls,

the substrate comprising a ball grid array substrate, and

the bonded connections of the chips to the substrate being provided by means selected from the following;

a) solder balls, and

b) gold bumps.

36. The method of claim 21 including forming the bonded connections between the top surface of the primary chip aside from the secondary chip to Tape Automated Bonding (TAB) leads.

25. A chip package for semiconductor chips including the steps as follows:

a printed circuit board with a window therethrough having a length and a width and a top surface and a bottom surface,

semiconductor chips including a primary chip and a secondary chip,

bonded connections between the top surface of the printed circuit board and the primary chip, with the primary chip overlying the window and which extends transversely across the width of the window,

the secondary chip being suspended within the window and having bonded connections between the secondary semiconductor chip and the primary chip in a chip-on-chip connection.

26. The package of claim 25 including:

the window having a width less than the length,

the primary chip and the secondary chip having substantially equal chip lengths and substantially equal chip widths.

27. The package of claim 25 including:

forming the bonded connections of the chips to the printed circuit boards by means selected from the following;

a) solder balls, and

b) gold bumps.

28. The package of claim 25 including:

forming the bonded connections of the chips to the printed circuit board by means selected from the following;

a) solder balls, and

b) gold bumps, and

forming big solder balls on the top surface of the printed circuit board,

the window having a width less than the length,

the primary chip and the secondary chip having substantially equal chip lengths and substantially equal chip widths

29. A method of forming a chip package for semiconductor chips including the steps as follows:

providing a substrate having a top surface and a bottom surface,

semiconductor chips including a primary chip and a secondary chip, the primary chip having a bottom surface and the secondary chip having a top surface,

forming bonded chip-on-chip connections between the top surface of the secondary chip and the bottom surface of the primary chip, and

forming bonded connections between the top surface of the substrate and the primary chip aside from the secondary chip leaving space between the secondary chip and the printed circuit board.

30. The method of claim 29 including:

the substrate comprising a ball grid array substrate, and

the bonded connections of the chips to the substrate being provided by means selected from the following;

a) solder balls, and

b) gold bumps.

32. A chip package for semiconductor chips including:

a substrate having a top surface and a bottom surface,

semiconductor chips including a primary chip and a secondary chip, the primary chip having a bottom surface and the secondary chip having a top surface,

bonded chip-on-chip connections between the top surface of the secondary chip and the bottom surface of the primary chip, and

bonded connections between the top surface of the substrate and the primary chip aside from the secondary chip leaving space between the secondary chip and the printed circuit board.

35. A method of interconnected semiconductor chips including the steps as follows:

semiconductor chips including a primary chip and a secondary chip, the primary chip having a top surface and the secondary chip having a bottom surface,

forming bonded chip-on-chip connections between the bottom surface of the secondary chip and the top surface of the primary chip, and

forming bonded connections between the top surface of the primary chip aside from the secondary chip.

37. A pair of interconnected semiconductor chips comprising:

a primary chip and a secondary chip, the primary chip having a top surface and the secondary chip having a bottom surface,

bonded chip-on-chip connections between the bottom surface of the secondary chip and the top surface of the primary chip, and

bonded connections between the top surface of the primary chip aside from the secondary chip.

38. The interconnected semiconductor chips of claim 37 including bonded connections between the top surface of the primary chip aside from the secondary chip to Tape Automated Bonding (TAB) leads.

39. A method of forming a chip package for semiconductor chips comprising:

forming a printed circuit board with a top surface and a window therethrough,

connecting at least two primary semiconductor chips each of which only partially overlies the window to the top surface of a printed circuit board by solder connections,

connecting a secondary semiconductor chip located within the window to at least of the two primary chips overlying the window in a chip-on-chip connection.

40. The method of claim 39 including connect big solder balls to the top surface of the printed circuit board aside from the primary semiconductor chips.

41. A chip package for semiconductor chips comprising:

a printed circuit board with a top surface and a window therethrough,

at least two primary semiconductor chips each of which only partially overlies the window connected to the top surface of the printed circuit board by solder connections,

a suspended secondary semiconductor chip located within the window, and

the suspended semiconductor chip being connected to at least of the two primary chips overlying the window in a chip-on-chip connection.

42. The package of claim 41 including big solder balls connected to the top surface of the printed circuit board aside from the primary semiconductor chips.

43. A method of forming a chip package for a semiconductor chip including the steps as follows:

forming a printed circuit board having a top surface and a bottom surface including a power structure and a ground structure which include;

a) a power bus and a ground bus, and

b) a power plane and a ground plane located within the printed circuit board,

forming solder connections between the printed circuit board and a plurality of chips overlying the printed circuit board in flip chip connections,

providing a bypass capacitor with a first terminal and a second terminal, and

connecting the first terminal of the bypass capacitor to the power structure and connecting the second terminal of the bypass capacitor to the ground structure, and

forming optional pads for connection to optional solder balls for functional selection.

44. A chip package for a semiconductor chip including:

a printed circuit board having a top surface and a bottom surface including a power structure and a ground structure which include;

a) a power bus and a ground bus, and

b) a power plane and a ground plane located within the printed circuit board,

solder connections between the printed circuit board and a plurality of chips overlying the printed circuit board in flip chip connections,

a bypass capacitor with a first terminal and a second terminal, and

connecting the first terminal of the bypass capacitor to the power structure and connecting the second terminal of the bypass capacitor to the ground structure, and

optional pads for connection to optional solder balls for functional selection.