Method and device for receiving sequential instructions

• US 20030197624A1
• Filed: 04/17/2002
• Published: 10/23/2003
• Est. Priority Date: 04/17/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Bresin, Giovanni
• Granted Patent: US 7,482,944 B2
• Time in Patent Office: Days
• US Class Current: 340/12.14
• CPC Class Codes: G08C 23/04 using light waves, e.g. infrared

Abstract

A method of receiving a plurality of instructions. The method generally comprises the steps of (A) storing a first of the instructions in response to receiving the first instruction at an initial time, and (B) rejecting a second of the instructions that depends from the first instruction in response to receiving the second instruction greater than a maximum delay after the initial time.

Claims

1. A method of receiving a plurality of instructions, comprising the steps of:

(A) storing a first of said instructions in response to receiving said first instruction at an initial time; and

(B) rejecting a second of said instructions that depends from said first instruction in response to receiving said second instruction greater than a maximum delay after said initial time.

2. The method according to claim 1, further comprising the step of rejecting said second instruction in response to receiving said second instruction less than a minimum delay after said initial time.

3. The method according to claim 2, wherein a difference between said maximum delay and said minimum delay is approximately a predetermined period.

4. The method according to claim 3, wherein said initial time is determined in units of said predetermined period.

5. The method according to claim 1, further comprising the step of calculating a new time in response to said initial time and said maximum delay.

6. The method according to claim 5, further comprising the step of calculating a second new time in response to accepting said second information.

7. The method according to claim 6, further comprising the step of rejecting a third of said instructions that depends from said first instruction in response to receiving said third instruction later than said second new time.

8. The method according to claim 1, further comprising the step of calculating said maximum delay in response to a predetermined multiplication factor and a period of said instructions.

9. The method according to claim 8, further comprising the step of rejecting said second instruction in response to a disable signal assigned to said first instruction.

10. The method according to claim 9, further comprising the steps of:

storing a third instruction that is independent of said first instruction in place of said first instruction in response to receiving said third instruction;

calculating a new time in response to receiving said third instruction;

storing said new time indexed by said third instruction;

accepting a repeat instruction of said instructions in response to receiving said repeat instruction proximate said new time.

11. A device comprising:

a detector circuit configured to receive a plurality of instructions; and

a timing circuit configured to (i) store a first of said instructions received at an initial time and (ii) reject a second of said instructions that depends from said first instruction in response to receiving said second instruction greater than a maximum delay after said initial time.

12. The device according to claim 11, wherein said timing circuit is further configured to reject said second instruction in response to receiving said second instruction less than a minimum delay after said initial time.

13. The device according to claim 12, wherein a difference between said maximum delay and said minimum delay is approximately a predetermined period.

14. The device according to claim 13, further comprising a clock circuit configured to generate a time signal in units of said predetermined period.

15. The device according to claim 11, further comprising a memory configured to store a new time determined by said initial time and said maximum time.

16. The device according to claim 15, wherein said timing circuit is further configured to calculate a second new time in response to acceptance of said second information.

17. The device according to claim 16, wherein said timing circuit is further configured to reject a third of said instructions that depends from said first instruction in response to receiving said third instruction later than said second new time.

18. The device according to claim 11, further comprising a memory configured to store (i) a predetermined multiplication factor and (ii) a period of said instructions that determine said maximum delay.

19. The device according to claim 18, wherein said memory is further configured to store a disable signal assigned to said first instruction to block acceptance of said second instruction.

20. The device comprising:

means for storing a first of a plurality of instructions in response to receiving said first instruction at an initial time;

means for rejecting a second of said instructions that depends from said first instruction in response to receiving said second instruction greater than a maximum delay after said initial time.