System and method for real-time spectrum analysis in a communication device

• US 20030198304A1
• Filed: 09/18/2002
• Published: 10/23/2003
• Est. Priority Date: 04/22/2002
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cognio, Inc. (Cisco Systems, Inc.)
• Inventors: Sugar, Gary L., Miller, Karl A., Baek, Jong Sup
• Granted Patent: US 6,714,605 B2
• Time in Patent Office: Days
• US Class Current: 375/340
• CPC Class Codes: G01R 13/0254 for triggering, synchronisation
• CPC Class Codes: H04L 1/1664 the supervisory signal being transmitted together with payload signals; piggybacking
• CPC Class Codes: H04W 16/14 Spectrum sharing arrangements between different networks
• CPC Class Codes: H04W 24/00 Supervisory, monitoring or testing arrangements
• CPC Class Codes: H04W 72/00 Local resource management

Abstract

A spectrum analysis engine (SAGE) that comprises a spectrum analyzer component, a signal detector component, a universal signal synchronizer component and a snapshot buffer component. The spectrum analyzer component generates data representing a real-time spectrogram of a bandwidth of radio frequency (RF) spectrum. The signal detector detects signal pulses in the frequency band and outputs pulse event information entries output, which include the start time, duration, power, center frequency and bandwidth of each detected pulse. The signal detector also provides pulse trigger outputs which may be used to enable/disable the collection of information by the spectrum analyzer and the snapshot buffer components. The snapshot buffer collects a set of raw digital signal samples useful for signal classification and other purposes. The universal signal synchronizer synchronizes to periodic signal sources, useful for instituting schemes to avoid interference with those signals.

Claims

1. A signal detector circuit comprising:

a. a peak detector that receives as input spectral information for successive time intervals of activity in a frequency band, detects one or more peaks in the spectral information and outputs information identifying peaks for each time interval; and

b. at least one pulse detector coupled to the peak detector, the pulse detector detects signal pulses that satisfy configurable characteristics based on the output of the peak detector.

2. The signal detector circuit of claim 1, wherein the peak detector detects a peak as power values above a threshold at a contiguous set of frequencies.

3. The signal detector circuit of claim 1, wherein the peak detector receives as input Fast Fourier Transform (FFT) values for a plurality of frequency bins and comprises a comparator that compares power at each frequency bin with a peak threshold to identify which frequency bins exceed the peak threshold.

4. The signal detector circuit of claim 3, wherein the peak detector identifies the maximum power value among a set of contiguous frequency bins that exceed the peak threshold.

5. The signal detector circuit of claim 3, wherein the pulse detector receives as input the information from the peak detector that identifies which frequency bins exceed the peak threshold and maximum power value for a set of contiguous frequency bins that exceed the peak threshold and determines whether that information satisfies the configurable characteristics.

6. The signal detector circuit of claim 5, wherein the pulse detector is configurable as to under what conditions a start of a pulse is to be detected and under what conditions a pulse is to be considered terminated.

7. The signal detector circuit of claim 5, wherein the pulse detector is configurable to detect the start of a pulse if a peak output by the peak detector is within minimum and maximum ranges for power, center frequency and bandwidth.

8. The signal detector circuit of claim 5, wherein the pulse detector is configurable to determine that a pulse has terminated if, after a pulse is detected, none of the detected peaks from the peak detector are within a predetermined amount from when the peak was originally detected with respect to power level, center frequency and bandwidth.

9. The signal detector circuit of claim 8, wherein the pulse detector outputs pulse information describing characteristics of a pulse if the duration of the pulse exceeds a duration threshold value.

10. The signal detector circuit of claim 5, wherein the pulse detector outputs pulse information for each detected pulse including center frequency, bandwidth and duration.

11. The signal detector circuit of claim 1, and comprising a plurality of pulse detectors each coupled to receive as input the output of the peak detector, wherein each pulse detector detects signal pulses that satisfy configurable characteristics based on the output of the peak detector.

12. The signal detector circuit of claim 11, wherein each pulse detector detects pulses that are any one or more of:

above a bandwidth threshold, within a range of center frequency, within a range of bandwidth and within a range of duration.

13. The signal detector of claim 11, and further comprising a control register for each pulse detector that stores controls to set the configurable characteristics for that pulse detector.

14. The signal detector of claim 11, wherein a pulse detector outputs a trigger signal in response to detecting a certain type of pulse.

15. A system comprising the signal detector of claim 11, and further comprising a storage buffer responsive to the trigger signal that stores digital signals representing samples of a received signal in the frequency band.

16. The system of claim 15, wherein the storage buffer further stores a timestamp signal identifying a time associated with an occurrence of the trigger signal.

17. The system of claim 15, wherein the storage buffer is a first-in-first-out buffer.

18. The system of claim 17, wherein the storage buffer continuously stores the digital signals while awaiting a next trigger signal.

19. The system of claim 17, wherein the storage buffer stores the digital signals only after the trigger signal.

20. A system comprising the signal detector of claim 1, and further comprising:

a. a Fast Fourier Transform (FFT) block that receives as input a digital signal representing activity in the frequency band and computes FFT values for a plurality of frequency bins for a time interval; and

b. a power calculation block coupled to the FFT block that computes the power at each frequency bin at each time interval, wherein the power is supplied as input to the peak detector and to the pulse detector.

21. The system of claim 20, and further comprising a memory that stores one or more of:

a. a running sum of the power at each frequency bin over time intervals;

b. a duty count comprising a running sum at each time interval of the number of times the power at each frequency bin exceeds the power threshold;

c. a maximum power for each frequency bin for the current and prior time intervals; and

d. a running count of the number of time intervals in which a certain number of peaks have been detected.

22. The system of claim 20, and further comprising a memory controller coupled to the memory, wherein a pulse detector outputs a trigger signal in response to detecting a certain type of pulse, and wherein the trigger signal is coupled to the memory controller to write to the memory the output of the power calculation block for one or more time intervals.

23. The system of claim 20, and further comprising an RF receiver that downconverts signals received in the frequency band to a baseband signal and an analog-to-digital converter coupled to the RF receiver that converts the baseband signal to a digital signal, wherein the RF receiver is configurable to operate in a wideband mode whereby it downconverts the entire frequency band, or a in a narrowband mode whereby it downconverts a portion of the frequency band.

24. A method for detecting signal pulses comprising steps of:

a. detecting one or more peaks in spectral information representing activity in a frequency band; and

b. detecting signal pulses that meet one or more characteristics from the detected one or more peaks.

25. The method of claim 24, wherein the step of detecting a peak comprises detecting power values above a threshold at a contiguous set of frequencies.

26. The method of claim 25, wherein the step of detecting a peak comprises detecting power values that exceed the threshold at contiguous Fast Fourier Transform (FFT) frequency bins.

27. The method of claim 24, and further comprising the step of providing for each detected peak, data including the maximum power value for each peak and frequency bins spanned by the peak.

28. The method of claim 24, wherein the step of detecting a signal pulse comprises examining, for each detected peak, one or more of a bandwidth, center frequency and duration and determining whether it is within ranges of those parameters to confirm it is a signal pulse that satisfies the configurable characteristics.

29. The method of claim 26, wherein the step of detecting a signal pulse comprises detecting, from the peaks, signal pulses of multiple types using an associated set of configurable ranges of bandwidth, center frequency and/or duration.

30. The method of claim 24, and further comprising the step of outputting for each detected signal pulse, one or more of the power, bandwidth, center frequency and duration of the signal pulse.

31. The method of claim 24, and further comprising the step of storing digital signals representing samples of a received signal when a pulse of a particular type is detected.

32. A processor readable medium encoded with instructions that, when executed by a processor, cause the processor to perform steps of:

a. detecting one or more peaks in spectral information representing activity in a frequency band; and

b. detecting signal pulses that meet one or more characteristics from the detected one or more peaks.

33. The processor readable medium of claim 32, wherein the instructions encoded on the medium for detecting one or more peaks comprises instructions for detecting power values above a threshold at a contiguous set of frequencies.

34. The processor readable medium of claim 33, wherein the instructions encoded on the medium for detecting one or more peaks comprises instructions for providing for each detected peak, data including the maximum power value for each peak and frequency bins spanned by the peak.

35. The processor readable medium of claim 32, wherein the instructions encoded on the medium for detecting a signal pulse comprise instructions for examining, for each detected peak, one or more of a bandwidth, center frequency and duration and determining whether it is within ranges of those parameters to confirm it is a signal pulse that satisfies the configurable characteristics.

36. The processor readable medium of claim 32, wherein the instructions encoded on the medium for detecting a signal pulse comprise instructions for detecting, from the peaks, signal pulses of multiple types using an associated set of configurable ranges of bandwidth, center frequency and/or duration.

37. The processor readable medium of claim 32, and further comprising instructions encoded on the medium for outputting for each detected signal pulse, one or more of the power, bandwidth, center frequency and duration of the signal pulse.

38. A system for synchronizing to a communication signal, comprising:

a. a clock module comprising;

i. at least N registers, each of which stores a programmable duration value associated with one of two states of a pulse of the communication signal, where N is equal to 2 times the number of pulses in a cycle of the communication signal;

ii. a down counter driven by a clock signal that counts down with each clock pulse from a value corresponding to the content of one of the N registers;

iii. a mod(N) counter coupled to the down counter that counts up to N−

1 by one in response to the down counter reaching zero and when Docket No.;

Cognio25US reaching N−

1, causing content of the next of the N registers to be loaded into the down counter;

b. a pulse detector circuit that detects a signal pulse in the communication signal;

and

c. a processor coupled to the clock module and to the signal detector circuit, wherein the processor examines the count values of the down counter and the mod(N) counter to measure a phase error between the clock signal used to drive the down counter and the pulse of the communication signal.

39. The system of claim 38, wherein the processor loads the N registers with values based on an expected frequency of one or more pulses of the communication signal.

40. The system of claim 38, wherein the processor generates a phase offset value according to the phase error it measures that is used to load a value into the down counter and the mod(N) counter when those counters count to zero in order to compensate for the phase error.

41. The system of claim 38, wherein the clock module comprises first, second, third and fourth registers, that store a duration value for a first, second, third and fourth state, respectively, of a pulse of a communication signal.

42. The system of claim 41, wherein the first register stores a duration value for the first state of a first pulse of the communication signal, the second register stores a duration value for the second state of the first pulse of the communication signal, the third register stores a duration value for the third state that corresponds to a first state of a second pulse of the communication signal and the fourth register stores a duration value for the fourth state that corresponds to a second state of the second pulse of the communication signal.

43. The system of claim 38, wherein the processor continues to monitor the count values of the down counter and the mod(N) counter to measure the phase error and generates a frequency offset value used for advancing or delaying counting of the down counter.

44. The system of claim 43, wherein the clock module further comprises a Z bit accumulator having a count input coupled to an output of the mod(N) counter, and a adder that adds an output of the accumulator with the frequency offset value and supplies the sum to an input of the accumulator, wherein a carry output of the accumulator is coupled the Nth register to increment or decrement the value of the Nth register before it is loaded into the down counter, extending or contracting the length of a cycle of the clock signal used to drive the down counter by one clock pulse every 2^Z/(frequency offset value) clock cycles.

45. The system of claim 43, wherein the processor updates the frequency offset over time using a loop filtering process.

46. The system of claim 43, wherein the processor updates the frequency offset using a second order phase locked loop process.

47. A method for synchronizing to a communication signal, comprising steps of:

a. detecting a pulse of the communication signal;

b. comparing the occurrence of the pulse with a local clock signal;

c. determining a phase error between the occurrence of the pulse and a state of the local clock signal; and

d. delaying or advancing the local clock signal by an amount corresponding to the phase error.

48. The method of claim 47, and further comprising the step of continuing to monitor the phase error between the occurrence of the pulse and the local clock signal and adjusting a frequency of the local clock signal based on the phase error.

49. The method of claim 48, and further comprising the step of updating the frequency offset over time using a loop filtering process.

50. The method of claim 48, and further comprising the step of updating the frequency offset over time using a second order loop filtering process.

51. A processor readable medium encoded with instructions that, when executed by a processor, cause the processor to perform steps of:

a. detecting a pulse of a communication signal;

b. comparing the occurrence of the pulse with a local clock signal;

c. determining a phase error between the occurrence of the pulse and a state of the local clock signal; and

d. delaying or advancing the local clock signal by an amount corresponding to the phase error.

52. The processor readable medium of claim 51, and further comprising instructions encoded on the medium for continuing to monitor the phase error between the occurrence of the pulse and the local clock signal and adjusting a frequency of the local clock signal based on the phase error.

53. The processor readable medium of claim 52, and further comprising instructions encoded on the medium for updating the frequency offset over time using a loop filtering process.

54. In a radio communication device that operates in a frequency band, a method for analyzing activity in the frequency band based on signals received by the communication device, comprising steps of:

a. computing Fast Fourier Transform (FFT) values at a plurality of frequency bins from a digital signal representing activity in a frequency band during a time interval;

b. computing the power at each frequency bin;

c. adding the power at each frequency bin for a current time interval with the power at the corresponding frequency bin for a previous time interval to obtain a running sum of the power at each frequency bin;

d. comparing the power at each frequency bin with a power threshold to obtain a duty count of the number of times that the power at each frequency bin exceeds the power threshold over time intervals; and

e. comparing the power at each frequency bin for a current time interval with the power at the corresponding frequency bin for a previous time interval to track the maximum power in each frequency bin over time intervals.

55. The method of claim 54, and further comprising the step of receiving a signal representing activity in the entire frequency band for a time interval, and converting the received signal to the digital signal.

56. The method of claim 54, and further comprising storing in a memory the running sum of power at each frequency bin, the duty count for each frequency bin and the maximum power for each frequency bin over time intervals.

57. The method of claim 54, and further comprising the step of comparing the power at each frequency bin with a peak threshold over multiple update cycles each of which comprises a plurality time intervals, thereby tracking the number of update cycles during which a certain number of peaks are detected.

58. The method of claim 57, and further comprising the step of storing the number of update cycles during which the certain number of peaks are detected.

59. A processor readable medium encoded with instructions that, when executed by a processor, cause the processor to perform steps of:

a. computing Fast Fourier Transform (FFT) values at a plurality of frequency bins from a digital signal representing activity in a frequency band during a time interval;

b. computing the power at each frequency bin;

c. adding the power at each frequency bin for a current time interval with the power at the corresponding frequency bin for a previous time interval to obtain a running sum of the power at each frequency bin;

d. comparing the power at each frequency bin with a power threshold to obtain a duty count of the number of times that the power at each frequency bin exceeds the power threshold over time intervals; and

e. comparing the power at each frequency bin for a current time interval with the power at the corresponding frequency bin for a previous time interval to track the maximum power in each frequency bin over time intervals.

60. A spectrum analysis device for use in a radio communication device that operates in a frequency band, comprising:

a. a Fast Fourier Transform (FFT) block that receives as input a digital signal representing activity in the frequency band for a time interval, wherein the FFT block computes FFT values for each of a plurality of frequency bins from the digital signal;

b. a power calculation block that computes the power at each frequency bin and outputs a power data field comprising power values for the plurality of frequency bins;

c. a signal detector circuit comprising;

i. a peak detector that receives as input the power data field for successive time intervals of activity in a frequency band, and detects one or more peaks in the spectral information, the peak detector outputting information identifying peaks for each time interval; and

ii. at least one pulse detector coupled to the peak detector that detects signal pulses that satisfy configurable characteristics based on the output of the peak detector.

61. The spectrum analysis device of claim 60, and further comprising a memory that stores one or more of:

a. a running sum of the power at each frequency bin over time intervals;

b. a duty count comprising a running sum at each time interval of the number of times the power at each frequency bin exceeds the power threshold;

c. a maximum power for each frequency bin for the current and prior time intervals; and

d. a running count of the number of time intervals in which a certain number of peaks have been detected.

62. A radio communication device comprising the spectrum analysis device of claim 60, and further comprising:

a. a radio frequency (RF) receiver that downconverts a received radio frequency signal and outputs a baseband signal; and

b. an analog-to-digital converter that converts the baseband signal to the digital signal representing activity in the frequency band for time intervals.

63. The radio communication device of claim 62, wherein the spectrum analysis device, RF receiver and analog-to-digital converter reside on a card device having an interface.

64. In combination, the radio communication device of claim 63, and a host device coupled to the card device via the interface, wherein the host device comprises a host processor and memory that stores programs that are used to process the output of the spectrum analysis device.

65. The combination of claim 64, and further comprising a display monitor that is coupled to the host device to display output of the spectrum analysis device, wherein the host device executes a program stored in the memory that generates data for the display of the output of the spectrum analysis device and user interface controls for the spectrum analysis device on the display monitor.

66. A system comprising the spectrum analysis device of claim 61, and further comprising a processor that examines information stored in the memory during operation of the spectrum analysis device to generally determine the type of activity occurring in the frequency band, and based thereon, generating information to configure one or more pulse detectors to detect one or more signal pulses of signals expected to be present in the frequency band.

67. The system of claim 66, wherein the processor further executes a program to generate data to display output of the spectrum analysis device, and well as a graphical user interface to control display of the output.

68. A system comprising the spectrum analysis device of claim 60, and further comprising:

a. a clock module comprising;

i. at least N registers, each of which stores a programmable duration value associated with one of two states of a pulse of the communication signal, where N is equal to 2 times the number of pulses in a cycle of the communication signal;

ii. a down counter driven by a clock signal that counts down with each clock pulse from a value corresponding to the content of one of the N registers;

iii. a mod(N) counter coupled to the down counter that counts up to N−

1 by one in response to the down counter reaching zero and when reaching N−

1, causing content of the next of the N registers to be loaded into the down counter;

b. a processor coupled to the clock module and to the signal detector circuit, wherein the processor examines the count values of the down counter and the mod(N) counter to measure a phase error between a clock signal used to drive the down counter and the pulse of the communication signal.

69. The system of claim 68, wherein the processor loads the N registers with values based on an expected frequency of one or more pulses of the communication signal.

70. The system of claim 68, wherein the processor generates a phase offset value according to the phase error it measures that is used to load a value into the down counter and the mod(N) counter when those counters count to zero in order to compensate for the phase error.

71. The system of claim 68, wherein the clock module comprises first, second, third and fourth registers, that store a duration value for a first, second, third and fourth state, respectively, of a pulse of a communication signal.

72. The system of claim 71, wherein the first register stores a duration value for the first state of a first pulse of the communication signal, the second register stores a duration value for the second state of the first pulse of the communication signal, the third register stores a duration value for the third state that corresponds to a first state of a second pulse of the communication signal and the fourth register stores a duration value for the fourth state that corresponds to a second state of the second pulse of the communication signal.

73. The system of claim 68, wherein the processor continues to monitor the count values of the down counter and the mod(N) counter to measure the phase error and generates a frequency offset value used for advancing or delaying counting of the down counter.

74. The system of claim 73, wherein the clock module further comprises a Z bit accumulator having an count input coupled to an output of the mod(N) counter, and a adder that adds an output of the accumulator with the frequency offset value and supplies the sum to an input of the accumulator, wherein a carry output of the accumulator is coupled the Nth register to increment or decrement the value of the Nth register before it is loaded into the down counter, extending or contracting the length of a the cycle of the clock signal used to drive the down counter by one clock pulse every 2^Z/(frequency offset value) clock cycles.

75. The system of claim 73, wherein the processor updates the frequency offset over time using a loop filtering process.

76. The system of claim 73, wherein the processor updates the frequency offset using a second order phase locked loop process.

77. A method for detecting radio signals in a frequency band comprising steps of:

a. operating a radio receiver in a wideband mode so as to generate a downconverted signal representing activity in the entire frequency band;

b. performing spectral analysis on the downconverted signal to generate spectral information of the frequency band; and

c. detecting signal pulses of signals expected to be present in the frequency band from the downconverted signal based on knowledge gained from the spectral information of the frequency band.

78. The method of claim 77, wherein the step of performing spectral analysis includes the step of computing the power at a plurality of frequency bins that span the frequency band.

79. The method of claim 77, wherein the step of detecting comprises examining the spectral information to detect a signal pulse that satisfies certain ranges of pulse duration, center frequency and/or bandwidth.

80. A processor readable medium encoded with instructions that, when executed by a processor, cause the processor to perform steps of:

a. computing a Fast Fourier Transform (FFT) values for each of a plurality of frequency bins from a digital signal representing activity in a frequency band for a time interval;

b. computing the power at each frequency bin from the FFT values;

c. detecting one or more peaks from the FFT values; and

d. detecting signal pulses that meet one or more characteristics from the detected one or more peaks.

81. The processor readable medium of claim 80, and further comprising instructions encoded on the medium that cause the processor to compute:

a. a running sum of the power at each frequency bin over time intervals;

b. a duty count comprising a running sum at each time interval of the number of times the power at each frequency bin exceeds a power threshold;

c. a maximum power for each frequency bin for the current and prior time intervals; and

d. a running count of the number of time intervals in which a certain number of peaks have been detected.

82. The processor readable medium of claim 80, and further comprising instructions encoded on the medium that, when executed, cause the processor to perform steps of:

a. comparing the occurrence of the pulse with a local clock signal;

b. determining a phase error between the occurrence of the pulse and a state of the local clock signal; and

c. delaying or advancing the local clock signal by an amount corresponding to the phase error.

83. The processor readable medium of claim 82, and further comprising instructions encoded on the medium that cause the processor to continue to monitor the phase error between the occurrence of the pulse and the local clock signal and adjusting a frequency of the local clock signal based on the phase error.

84. The processor readable medium of claim 82, and further comprising instructions encoded on the medium for updating the frequency offset over time using a loop filtering process.