Method of manufacturing a semiconductor device

• US 20030199122A1
• Filed: 05/16/2003
• Published: 10/23/2003
• Est. Priority Date: 11/29/1999
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Systems Company Limited (Hitachi, Ltd.)
• Inventors: Masuda, Masachika, Wada, Tsutomu
• Granted Patent: US 6,797,539 B2
• Time in Patent Office: Days
• US Class Current: 438/113
• CPC Class Codes: H01L 21/44 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2223/54406 comprising alphanumeric information
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85203 Thermocompression bonding
• CPC Class Codes: H01L 2224/85205 Ultrasonic bonding
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

For the manufacturing of semiconductor devices, in which multiple semiconductor chips which are mounted on a wiring substrate are processed for block molding and thereafter the wiring substrate is diced into individual resin-molded semiconductor devices, here is disclosed a technique for finding out easily, even after the dicing process, the position of each resin-molded semiconductor device in its former state on the wiring substrate. It includes processing steps of implementing the block molding with resin for multiple semiconductor chips mounted on a wiring substrate and thereafter dicing the wiring substrate into individual resin-molded semiconductor devices, with the substrate dicing step being preceded by a step of appending an address information pattern to each of the resin-molded semiconductor devices.

Claims

1. A method of manufacturing a semiconductor device including processing steps of implementing the block molding with resin for a plurality of semiconductor chips which are mounted on a wiring substrate and thereafter dicing the wiring substrate into a plurality of resin-molded semiconductor devices,

wherein said method further includes a step, which precedes said substrate dicing step, of appending address information to each of the resin-molded semiconductor devices.

2. A method of manufacturing a semiconductor device according to claim 1, wherein said address information includes information indicative of the position of each of the resin-molded semiconductor devices within the wiring substrate.

3. A method of manufacturing a semiconductor device including processing steps of implementing the block molding with resin for a plurality of semiconductor chips which are mounted on a wiring substrate and thereafter dicing the wiring substrate into a plurality of resin-molded semiconductor devices,

wherein said method further includes a step, which precedes said substrate dicing step, of appending address information of each of the resin-molded semiconductor devices to part of the wiring substrate.

4. A method of manufacturing a semiconductor device according to claim 3, wherein said address information is shaped in a wiring material which has been formed in a step of forming wire patterns on the wiring substrate.

5. A method of manufacturing a semiconductor device according to claim 4, wherein said address information also has the role of index information which orients the resin-molded semiconductor device on a circuit board at packaging.

6. A method of manufacturing a semiconductor device according to claim 4, wherein said address information is shaped at a position different from the position of index information which orients the resin-molded semiconductor device on a circuit board at packaging.

7. A method of manufacturing a semiconductor device including processing steps of implementing the block molding with resin for a plurality of semiconductor chips which are mounted on a wiring substrate and thereafter dicing the wiring substrate into a plurality of resin-molded semiconductor devices,

wherein said method further includes a step, which precedes said substrate dicing step that follows the block molding with resin of said semiconductor chips, of appending address information to each of the resin-molded semiconductor devices.

8. A method of manufacturing a semiconductor device according to claim 7, wherein said address information is shaped in a step of printing a mark on the surface of the resin mold.

9. A method of manufacturing a semiconductor device according to claim 8, wherein said address information and said mark are printed based on a laser printing scheme.

10. A method of manufacturing a semiconductor device according to claim 7, wherein said address information is shaped in a step different from a step of printing the mark on the resin mold.

11. A method of manufacturing a semiconductor device comprising processing steps of dividing semiconductor chips which are mounted on a wiring substrate into blocks and molding the chips with resin and thereafter dicing each of the blocks into a plurality of resin-molded semiconductor devices.

12. A method of manufacturing a semiconductor device according to claim 11 further including a step, which precedes said block dicing step, of appending address information to each of the resin-molded semiconductor devices.

13. A method of manufacturing a semiconductor device according to claim 11, wherein said address information includes information indicative of the position of each of the resin-molded semiconductor devices in the block.

14. A method of manufacturing a semiconductor device according to claim 11, wherein said address information is shaped in advance of said step of molding the semiconductor chips with resin.

15. A method of manufacturing a semiconductor device according to claim 11, wherein said address information is shaped after said step of molding the semiconductor chips with resin.