Computer system and method that eliminates the need for an operating system

• US 20030200354A1
• Filed: 05/23/2003
• Published: 10/23/2003
• Est. Priority Date: 01/26/2001
• Status: Active Grant

• Current Assignee: Syed Kamal H. Jaffrey
• Original Assignee: Syed Kamal H. Jaffrey
• Inventors: Jaffrey, Syed Kamal H.
• Granted Patent: US 7,197,626 B2
• Time in Patent Office: Days
• US Class Current: 719/321
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files

Abstract

A hardware/firmware layer comprising a Device Manager, an Information Manager, a Memory Manager, and a Process Manager contained in one or more semiconductor chips is disclosed. The hardware/firmware layer eliminates the need for an operating system. Each of the Managers comprises a microcontroller associated with a firmware embedded in ROM or Flash memory that contains instruction sets that cause the microcontroller to provide a designated task of device management, information management, memory management and process management. In another aspect of the invention, devices connected to the computer system are “smart devices,” each device having a device microcontroller and embedded device drivers in a ROM or Flash memory. The hardware/firmware of the present invention does not need to search for available devices, provide diagnostic tests or obtain device drivers to communicate with the devices. Instead, the device microcontroller uses the embedded device driver to perform configuration and self diagnostic test as well as device operations. If the device is operational, the device microcontroller sends an identification signal to the hardware/firmware layer of the present to indicate availability of the device.

Claims

1. A computer system that eliminates a need for an operating system comprising:

a central processing unit (CPU);

a main memory;

a further unit that includes

a first microcontroller and

a first memory containing a first set of instructions configured to cause the microcontroller to manage CPU operations; and

a plurality of trace links connecting the further unit to the CPU and the main memory to facilitate communication between the further unit, the CPU and the main memory.

2. The computer system as in claim 1, wherein the system further comprises:

at least one device, a trace link connecting the device to the further unit; and

the further unit further includes

a second microcontroller; and

a second memory containing a second set of instructions configured to cause the second microcontroller to manage the device.

3. The computer system as in claim 2, further comprising:

the further unit further includes

a third microcontroller; and

a third memory containing a third set of instructions configured to cause the third microcontroller to manage memory operations.

4. The computer system as in claim 3, further comprising:

the further unit further includes

a fourth controller; and

a fourth memory containing a fourth set of instructions configured to cause the fourth controller to manage data operations.

5. The computer system as in claim 4, wherein the plurality of microcontrollers in the further units are connected together to communicate with each other.

6. The computer system as in claim 5, further comprising:

the further unit includes

a cross-bar switch to connect the plurality of microcontrollers.

7. The computer system as in claim 2, further comprising:

the device includes

a fifth microcontroller; and

a fifth memory containing a fifth set of instructions configured to cause the fifth microcontroller to control the device operations, the fifth microcontroller in communication with at least the second microcontroller.

8. The computer system as in claim 7, further comprising:

the fifth set of instructions in the fifth memory further configured to cause the fifth microcontroller to test the device and if the device is operational the fifth set of instructions is configured to cause the fifth microcontroller to signal at least the second microcontroller to indicate availability of the device.

9. The computer system as in claim 8, further comprising:

the fifth set of instructions in the fifth memory further configured to cause the fifth microcontroller to signal at least the second microcontroller to indicate availability of the device includes sending device identification and required resource data.

10. The computer system as in claim 9, further comprising:

the second set of instructions in the second memory further configured to cause the second microcontroller to receive the signal indicating availability of the device and allocating available resources to the device.

11. An apparatus for managing computer operations comprising:

a first microcontroller; and

a first memory containing a first set of instructions configured to cause the microcontroller to manage central processing unit (CPU) operations.

12. The apparatus as in claim 11, wherein the apparatus further comprises:

a second microcontroller; and

a second memory containing a second set of instructions configured to cause the second microcontroller to manage device operations.

13. The apparatus as in claim 12, further comprising:

a third microcontroller; and

a third memory containing a third set of instructions configured to cause the third microcontroller to manage memory operations.

14. The apparatus as in claim 13, further comprising:

a fourth controller; and

a fourth memory containing a fourth set of instructions configured to cause the fourth controller to manage data operations.

15. The apparatus as in claim 14, wherein the plurality of microcontrollers are connected together to communicate with each other.

16. The apparatus as in claim 15, further comprising:

a cross-bar switch to connect the plurality of microcontrollers.

17. The apparatus as in claim 14, wherein the memory is a read only memory (ROM).

18. The apparatus as in claim 14, wherein the memory is an erasable programmable ROM (EPROM).

19. The apparatus as in claim 14, wherein the memory is a Flash memory.

20. The apparatus as in claim 14, wherein the microcontrollers are digital signal processors (DSPs).

21. The apparatus as in claim 15, wherein the apparatus is contained in a semiconductor chip.

22. The apparatus as in claim 12, further comprising:

a device including

a fifth microcontroller; and

a fifth memory containing a fifth set of instructions configured to cause the fifth microcontroller to control the device operations, the fifth microcontroller in communication with at least the second microcontroller.

23. The apparatus as in claim 22, further comprising:

the fifth set of instructions in the fifth memory further configured to cause the fifth microcontroller to test the device and if the device is operational the fifth set of instructions is configured to cause the fifth microcontroller to signal at least the second microcontroller to indicate availability of the device.

24. The apparatus as in claim 23, further comprising:

the fifth set of instructions in the fifth memory further configured to cause the fifth microcontroller to signal at least the second microcontroller to indicate availability of the device includes sending device identification and required resource data.

25. The apparatus as in claim 24, further comprising:

the second set of instructions in the second memory further configured to cause the second microcontroller to receive the signal indicating availability of the device and allocating available resources to the device.

26. A device for use in a computer system that eliminates a need for an operating system comprising:

device circuitry

a first microcontroller; and

a memory containing a set of instructions configured to cause the microcontroller to control device circuitry, the instructions further configured to facilitate the microcontroller to communicate with a second microcontroller that manages a central processing unit (CPU) operation.