Method, apparatus, and system for maintaining conflict-free memory address space for input/output memory subsystems

• US 20030200358A1
• Filed: 04/19/2002
• Published: 10/23/2003
• Est. Priority Date: 04/19/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Brown, Mark L., Luse, Paul E.
• Granted Patent: US 6,823,421 B2
• Time in Patent Office: Days
• US Class Current: 710/5
• CPC Class Codes: G06F 13/404 with address mapping

Abstract

According to one embodiment of the present invention, an apparatus is provided which includes a first address translation unit and a second address translation unit. The first address translation unit is programmed for a minimum amount of memory addresses required to accept control transactions on a first bus. The second address translation unit is programmed to a memory address range that corresponds to an amount of local memory for caching operations between the first I/O processor and a first I/O interconnect device and an amount of memory space required by the I/O interconnect device. The apparatus includes logic to determine, upon receiving an incoming host request, whether a reply address corresponding to the host request overlaps with the memory address range programmed for the second address translation unit. The apparatus further includes logic to dynamically alter a data flow between the first I/O interconnect device and the host such that data from the first I/O interconnect device is transferred to host via the local memory of the first I/O processor, if the reply address overlaps with the memory address range for the second address translation unit.

Claims

1. A method comprising:

programming a first address translation unit in a first input/output (I/O) processor for a minimum amount of memory addresses required to accept control transactions on a first bus;

programming a second address translation unit in the first I/O processor to a memory address range that corresponds to an amount of local memory for caching operations between the first I/O processor and a first I/O interconnect device and an amount of memory required by the first I/O interconnect device;

in response to an incoming host request being received from a host, determining whether the host request'"'"'s reply address overlaps with the memory address range for the second address translation unit; and

if the host request'"'"'s reply address overlaps with the memory address range, dynamically changing a data flow between the first I/O interconnect device and the host such that data from the first I/O interconnect device is transferred to the host via the local memory of the first I/O processor.

2. The method of claim 1 further including:

if the host request'"'"'s reply address does not overlap with the memory address range programmed for the second address translation unit, maintaining a standard data flow between the first I/O interconnect device and the host such that data from the first I/O interconnect device is transferred to the host via a first bridge.

3. The method of claim 1 wherein dynamically changing the data flow between the first I/O interconnect device and the host includes:

setting up a reply buffer in the local memory of the first I/O processor to receive data from the first I/O interconnect device.

4. The method of claim 3 further including:

passing the host request to the first I/O interconnect device.

5. The method of claim 4 further including:

transferring data from the first I/O interconnect device to the local memory of the first I/O processor.

6. The method of claim 5 further including:

transferring data from the local memory of the first I/O processor to the host via the first address translation unit.

7. The method of claim 2 wherein maintaining the standard data flow includes:

passing the host request to the first I/O interconnect device; and

transferring data from the first I/O interconnect device to the host via the first bridge.

8. The method of claim 7 wherein the first bride is coupled to the host via a first bus and coupled to the first I/O interconnect device via a second bus.

9. The method of claim 8 wherein the first bus is a primary peripheral component interconnect (PCI) bus, the second bus is a secondary PCI bus, and the first bridge is a PCI-to-PCI bridge.

10. The method of claim 1 wherein the first address translation unit is configured as the primary address translation unit for the first I/O processor.

11. The method of claim 1 wherein the second address translation unit is configured as the secondary address translation unit for the first I/O processor.

12. An apparatus comprising:

a first address translation unit programmed for a minimum amount of memory addresses required to accept control transactions on a first bus;

a second address translation unit programmed to a memory address range that corresponds to an amount of local memory for caching operations between the first I/O processor and a first I/O interconnect device and an amount of memory required by the first I/O interconnect device;

logic to determine, upon receiving an incoming host request, whether a reply address corresponding to the host request overlaps with the memory address range programmed for the second address translation unit; and

logic to dynamically alter a data flow between the first I/O interconnect device and the host such that data from the first I/O interconnect device is transferred to host via the local memory of the first I/O processor, if the reply address overlaps with the memory address range for the second address translation unit.

13. The apparatus of claim 12 further including:

logic to maintain a standard data flow between the first I/O interconnect device and the host such that data from the first I/O interconnect device is transferred to the host via a first bridge, if the reply address does not overlap with the memory address range for the second address translation unit.

14. The apparatus of claim 12 wherein logic to dynamically alter the data flow between the first I/O interconnect device and the host includes:

logic to set up a reply buffer in the local memory of the first I/O processor to receive data from the first I/O interconnect device.

15. The apparatus of claim 14 further including:

logic to pass the host request to the first I/O interconnect device.

16. The apparatus of claim 15 further including:

logic to transfer data from the first I/O interconnect device to the local memory of the first I/O processor.

17. The apparatus of claim 16 further including:

logic to transfer data from the local memory of the first I/O processor to the host via the first address translation unit.

18. The apparatus of claim 17 wherein logic to maintain the standard data flow includes:

logic to pass the host request to the first I/O interconnect device; and

logic to transfer data from the first I/O interconnect device to the host via the first bridge.

19. The apparatus of claim 18 wherein the first bride is coupled to the host via a first bus and coupled to the first I/O interconnect device via a second bus.

20. The apparatus of claim 19 wherein the first bus is a primary peripheral component interconnect (PCI) bus, the second bus is a secondary PCI bus, and the first bridge is a PCI-to-PCI bridge.

21. The apparatus of claim 12 wherein the first address translation unit is configured as the primary address translation unit for the first I/O processor.

22. The apparatus of claim 12 wherein the second address translation unit is configured as the secondary address translation unit for the first I/O processor.

23. A system comprising:

a host processor coupled to transmit data to and receive data from one or more input/output (I/O) devices; and

an input/output (I/O) processor coupled to the host processor via a host bus to manage input/output operations with respect to the one or more I/O devices, the I/O processor including;

a first address translation unit programmed for a minimum amount of memory addresses required to accept control transactions on a first bus;

a second address translation unit programmed to a memory address range that corresponds to an amount of local memory for caching operations between the I/O processor and a first I/O interconnect device and an amount of memory required by the first I/O interconnect device;

logic to determine, upon receiving an incoming host request, whether a reply address corresponding to the host request overlaps with the memory address range programmed for the second address translation unit; and

logic to dynamically alter a data flow between the first I/O interconnect device and the host processor such that data from the first I/O interconnect device is transferred to host processor via the local memory of the I/O processor, if the reply address overlaps with the memory address range for the second address translation unit.

24. The system of claim 23 wherein the I/O processor further includes:

logic to maintain a standard data flow between the first I/O interconnect device and the host such that data from the first I/O interconnect device is transferred to the host via a first bridge, if the reply address does not overlap with the memory address range for the second address translation unit.

25. The system of claim 23 wherein logic to dynamically alter the data flow between the first I/O interconnect device and the host includes:

logic to set up a reply buffer in the local memory of the I/O processor to receive data from the first I/O interconnect device;

logic to pass the host request to the first I/O interconnect device;

logic to transfer data from the first I/O interconnect device to the local memory of the I/O processor; and

logic to transfer data from the local memory of the I/O processor to the host via the first address translation unit.

26. The system of claim 24 wherein logic to maintain the standard data flow includes:

logic to pass the host request to the first I/O interconnect device; and

logic to transfer data from the first I/O interconnect device to the host via the first bridge.

27. The system of claim 26 wherein the first bride is coupled to the host via a first bus and coupled to the first I/O interconnect device via a second bus.

28. The system of claim 27 wherein the first bus is a primary peripheral component interconnect (PCI) bus, the second bus is a secondary PCI bus, and the first bridge is a PCI-to-PCI bridge.

29. The system of claim 23 wherein the first address translation unit is configured as the primary address translation unit for the I/O processor and wherein the second address translation unit is configured as the secondary address translation unit for the I/O processor.