Intermediate-grain reconfigurable processing device

• US 20030200418A1
• Filed: 11/12/2002
• Published: 10/23/2003
• Est. Priority Date: 04/11/1996
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: DeHon, Andre, Mirsky, Ethan, Knight,, Thomas F. Jr.
• Granted Patent: US 6,684,318 B2
• Time in Patent Office: Days
• US Class Current: 712/15
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus

Abstract

A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.

Claims

1. A programmable integrated circuit comprising:

logic units which perform operations on data in response to instructions of a defined set of instructions;

memories which store and retrieve data in response to received addresses;

a configurable interconnect which provides signal transmission between the logic units and memories, the interconnect being configurable from configuration control data; and

programmable configuration storage for storing the configuration control data.