System and method for temporally isolating environmentally sensitive integrated circuit faults
First Claim
1. A method for temporally isolating a fault within an integrated circuit comprising the steps of:
- determining a marginally failing environmental condition associated with the fault;
determining a clock cycle at which the fault was first detected; and
applying a plurality of first test pattern subsets under the marginally failing environmental condition, wherein each first test pattern subset is applied from an initial clock cycle through a unique candidate clock cycle.
2 Assignments
0 Petitions
Accused Products
Abstract
A procedure for temporally isolating an environmentally dependent integrated circuit fault includes the steps of determining a marginally failing and a minimally passing environmental condition corresponding to the fault; identifying a clock cycle Tmax at which the fault was first detected; determining a candidate clock cycle at which the fault may have occurred; and iteratively a) applying test pattern subsets from an initial clock cycle through the candidate clock cycle under the marginally failing environmental condition; b) applying remaining test patterns under the minimally passing environmental condition; and c) adjusting the candidate clock cycle based upon whether the fault occurred during test pattern subset application up through the candidate clock cycle under the marginally failing environmental condition. Candidate clock cycle adjustment in accordance with a binary search technique enables determination of an exact clock cycle at which the fault occurred in a maximum of Log2 (Tmax+1) iterations.
16 Citations
20 Claims
-
1. A method for temporally isolating a fault within an integrated circuit comprising the steps of:
-
determining a marginally failing environmental condition associated with the fault;
determining a clock cycle at which the fault was first detected; and
applying a plurality of first test pattern subsets under the marginally failing environmental condition, wherein each first test pattern subset is applied from an initial clock cycle through a unique candidate clock cycle. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. A method for temporally isolating a fault within an integrated circuit comprising the steps of:
-
determining a marginally failing environmental condition associated with the fault;
identifying a clock cycle Tmax at which the fault was first detected;
determining a candidate clock cycle at which the fault may have occurred;
iteratively performing the substeps of;
applying test pattern subsets from an initial clock cycle through the candidate clock cycle under the marginally failing environmental condition; and
adjusting the candidate clock cycle based upon whether the fault occurred during test pattern subset application;
and determining an exact clock cycle at which the fault occurred in a maximum of Log2 (Tmax+1) substep iterations.
-
-
14. A method for temporally isolating a fault within an integrated circuit comprising the steps of:
-
determining a marginally failing environmental condition associated with the fault;
determining an upper bound clock cycle corresponding to a latest clock cycle at which the fault may have occurred;
determining a lower bound clock cycle corresponding to an earliest clock cycle at which the fault may have occurred;
determining a candidate clock cycle at which the fault may have occurred;
applying a test pattern subset from an initial clock cycle through the candidate clock cycle under the marginally failing environmental condition; and
adjusting the candidate clock cycle and one from the group of the upper bound clock cycle and the lower bound clock cycle based upon whether the fault occurred during test pattern subset application. - View Dependent Claims (15, 16, 17, 18, 19, 20)
-
Specification