Array-based architecture for molecular electronics

• US 20030200521A1
• Filed: 01/17/2003
• Published: 10/23/2003
• Est. Priority Date: 01/18/2002
• Status: Active Grant

• Current Assignee: California Institute of Technology, President and Fellows of Harvard College (Harvard Corporation)
• Original Assignee: California Institute of Technology, President and Fellows of Harvard College (Harvard Corporation)
• Inventors: Lieber, Charles M., DeHon, Andre
• Granted Patent: US 7,073,157 B2
• Time in Patent Office: Days
• US Class Current: 716/16
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 2213/81 Array wherein the array conductors, e.g. word lines, bit lines, are made of nanowires
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H10K 10/46 Field-effect transistors, e.g. organic thin-film transistors [OTFT] H10K10/43 takes precedence
• CPC Class Codes: H10K 10/701 Organic molecular electronic devices
• CPC Class Codes: H10K 19/00 Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
• CPC Class Codes: H10K 19/202 Integrated devices comprising a common active layer

Abstract

An architecture for nanoscale electronics is disclosed. The architecture comprises arrays of crossed nanoscale wires having selectively programmable crosspoints. Nanoscale wires of one array are shared by other arrays, thus providing signal propagation between the arrays. Nanoscale signal restoration elements are also provided, allowing an output of a first array to be used as an input to a second array. Signal restoration occurs without routing of the signal to non-nanoscale wires.

Claims

1. An architecture for nanoscale electronics comprising:

arrays of crossed nanoscale wires, each array comprising a plurality of crosspoints between nanoscale wires, the crosspoints being selectively programmable, wherein nanoscale wires of one array are shared by other arrays, thus providing signal propagation between the one array and the other arrays; and

nanoscale signal restoration elements, allowing an output of a first array to be used as an input to a second array, wherein signal restoration occurs without routing of the signal to non-nanoscale wires.

2. The architecture of claim 1, wherein the crosspoints are programmable to connect the nanoscale wires forming the crosspoints.

3. The architecture of claim 1, wherein the crosspoints are programmable to gate the nanoscale wires forming the crosspoints.

4. The architecture of claim 1, further comprising nanoscale driving devices of crossed nanoscale wires for the arrays, the crosspoints being programmable by means of the nanoscale driving devices.

5. The architecture of claim 1, further comprising power supply gating crossbars having a set of crossed nanoscale wires, wherein a first set of nanoscale wires is connected to a power supply and a second, orthogonal, set of nanoscale wires controls resistance along the first set of nanoscale wires.

6. The architecture of claim 4, further comprising non-nanoscale wires transmitting input signals to the driving devices.

7. The architecture of claim 6, wherein the non-nanoscale wires are microscale wires.

8. The architecture of claim 1, wherein the crosspoints are programmable to exhibit a bi-stable behavior.

9. The architecture of claim 8, wherein a first state of the crosspoints corresponds to a weak conductance state and a second state of the crosspoints corresponds to a strong conductance state between the nanoscale wires forming the crosspoints.

10. The architecture of claim 8, wherein a crosspoint consists of a first nanoscale wire crossed with a second nanoscale wire, a first state of the crosspoint corresponding to the first nanoscale wire controlling the second nanoscale wire, and a second state of the crosspoint corresponding to the first nanoscale wire not controlling the second nanoscale wire.

11. The architecture of claim 10, wherein, in the first state of the crosspoint, voltage on the first nanoscale wire controls conductance through the second nanoscale wire.

12. The architecture of claim 1, wherein the crosspoints comprise diode-type crosspoints.

13. The architecture of claim 1, wherein the crosspoints comprise FET-type crosspoints.

14. The architecture of claim 13, wherein the FET-type crosspoints are programmed during fabrication.

15. The architecture of claim 14, wherein programming of the FET-type crosspoints is obtained through selective stamping.

16. The architecture of claim 12, wherein programming of at least a portion of the crosspoints is performed after fabrication.

17. The architecture of claim 16, wherein said programming is performed electrically.

18. The architecture of claim 13, wherein programming of at least a portion of the crosspoints is performed after fabrication.

19. The architecture of claim 18, wherein said programming is performed electrically.

20. The architecture of claim 1, wherein the nanoscale signal restoration elements comprise arrays having FET-type crosspoints.

21. The architecture of claim 20, wherein arrays having non-restoring logic elements are connected to arrays with signal restoring elements, such that a nanoscale restoring logic is obtained.

22. The architecture of claim 5, wherein the power supply gating crossbars act as open circuit during operation of the arrays.

23. The architecture of claim 5, wherein the power supply gating crossbars act as a low resistance device during operation of the arrays.

24. The architecture of claim 5, wherein the power supply gating crossbars act as a controllable resistance device during operation of the arrays.

25. The architecture of claim 5, wherein the power supply gating crossbars act as a static pull-up during operation of the arrays.

26. The architecture of claim 5, wherein the power supply gating crossbars act as a static pull-down during operation of the arrays.

27. The architecture of claim 5, wherein the power supply gating crossbars act as a precharge or evaluate gate during operation of the arrays.

28. The architecture of claim 1, wherein a logical signal produced as output in one array is switched through the nanoscale wires and crosspoints to become an input to another array.

29. The architecture of claim 1, wherein arbitrary signal routing is provided.

30. The architecture of claim 29, wherein arbitrary signal routing is provided by means of a Manhattan routing.

31. The architecture of claim 29, wherein arrays performing logic functions and signal restoration also perform switching to enable routing.

32. The architecture of claim 1, wherein signal polarity control is obtained through arrangement of array inversions.

33. The architecture of claim 1, further comprising means for interfacing with non-nanoscale inputs and outputs.

34. The architecture of claim 1, wherein the nanoscale wires comprise silicon nanowires.

35. The architecture of claim 1, wherein the nanoscale wires comprise carbon nanotubes.

36. The architecture of claim 1, wherein the nanoscale wires comprise silicon nanowires and carbon nanotubes.

37. The architecture of claim 1, wherein defects in the architecture are avoided by post fabrication configuration.

38. The architecture of claim 5, wherein the power supply gating crossbars have a first condition in which they selectively drive internal lines of core arrays, and a second condition in which they provide a connection to the power supply in order to enable the signal restoration elements.

39. The architecture of claim 1, wherein the nanoscale wires comprise a first set of nanoscale wires having an oxide cover and a second set of nanoscale wires not having an oxide cover.

40. The architecture of claim 39, wherein each wire crossing between a nanometer-scale wire of the first set of nanometer-scale wires and a nanometer-scale wire of the second set of nanometer-scale wires is able to exhibit a Field-Effect-Transistor (FET) behavior.

41. The architecture of claim 5, wherein the power supply crossbars serve as decoders allowing selective addressing of individual array wires.

42. The architecture of claim 41, wherein the selective addressing is used to program individual array crosspoints.

43. The architecture of claim 42, wherein programming of individual array crosspoints is used to define the logic functionality of the array.

44. The architecture of claim 42, wherein programming of individual array crosspoints is used to define routing of signals among arrays.

45. The architecture of claim 42, wherein programming of individual array crosspoints allows arrays to be programmed to avoid defective components.

46. The architecture of claim 41, wherein the decoders are provided with additional encoding lines.

47. The architecture of claim 41, wherein each decoder comprises N nanoscale wires connected with the arrays and 2log₂(N)+1 nanoscale wires connected with non-nanoscale wires.

48. The architecture of claim 41, wherein the decoders comprise a decoder pattern, the decoder pattern being customized during fabrication of the decoders.

49. The architecture of claim 1, wherein the arrays comprise a first array and a second array, the first array having an output and the second array having an input, wherein the output of the first array is the input of the second array and wherein the second array is placed orthogonally to the first array.

50. The architecture of claim 1, wherein the arrays further include spare arrays.

51. The architecture of claim 1, wherein faulty arrays are avoidable by signal routing through the arrays.

52. The architecture of claim 1, wherein faulty arrays are avoidable by post fabrication configuration of signal routing through the array.

53. The architecture of claim 1, wherein one or more of the arrays serve as memory arrays.

54. A circuit comprising:

a plurality of arrays having first and second sets of address lines and connections between the first and second sets of address lines; and

a plurality of driving devices for the plurality of arrays, the driving devices having third and fourth sets of address lines and connections between the third and fourth sets of address lines,

wherein the driving devices have a first condition in which they act as decoders for the arrays, and a second condition in which they act as signal restoring devices for the arrays.

55. A method of driving a plurality of arrays having first and second sets of address lines and connections between the first and second sets of address lines, the method comprising:

providing a plurality of driving devices for the plurality of arrays, the driving devices having third and fourth sets of address lines and connections between the third and fourth sets of address lines, the driving devices having a first condition in which the driving devices act as decoders for the arrays, and a second condition in which the driving devices act as signal restoring devices for the arrays.

56. A method for assembly of arbitrary boolean logic computations at sublithographic scales, the method comprising:

providing sublithographic-scale arrays performing a predetermined logic function;

interconnecting the arrays; and

customizing the arrays to perform the logic function and signal routing.

57. The method of claim 56, wherein the arrays are cascaded through sublithographic interconnections.

58. The method of claim 56, wherein the logic is programmable after fabrication.

59. The method of claim 56, wherein the signal routing is programmable after fabrication.

60. The method of claim 56, wherein portions of the logic are specified during fabrication.

61. The method of claim 56, wherein portions of the routing are specified during fabrication.

62. The method of claim 56, wherein the logic is tolerant to defects in assembly.

63. The method of claim 56, wherein the logic is programmable after fabrication to tolerate defects in assembly.

64. The method of claim 56, wherein signal routing is programmable after fabrication to tolerate defects in assembly.