Semiconductor device and method of manufacturing the same

• US 20030201439A1
• Filed: 05/28/2003
• Published: 10/30/2003
• Est. Priority Date: 02/12/1999
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Osame, Mitsuaki, Murakami, Satoshi, Ohnuma, Hideto, Koyama, Jun, Yamazaki, Shunpei, Kitakado, Hidehito, Tanaka, Yukio, Fujimoto, Etsuko
• Granted Patent: US 7,288,789 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H10K 50/8426 Peripheral sealing arrangements, e.g. adhesives, sealants
• CPC Class Codes: H10K 50/865 comprising light absorbing layers, e.g. light-blocking layers
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/1216 the pixel elements being capacitors
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/126 Shielding, e.g. light-blocking means over the TFTs
• CPC Class Codes: H10K 59/8722 Peripheral sealing arrangements, e.g. adhesives, sealants

Abstract

A semiconductor device in which TFT'"'"'s of suitable structures are arranged depending upon the performances of the circuits, and storage capacitors are formed occupying small areas, the semiconductor device featuring high performance and bright image. The thickness of the gate-insulating film is differed depending upon a circuit that gives importance to the operation speed and a circuit that gives importance to the gate-insulating breakdown voltage, and the position for forming the LDD region is differed depending upon the TFT that gives importance to the countermeasure against the hot carriers and the TFT that gives importance to the countermeasure against the off current. This makes it possible to realize a semiconductor device of high performance. Further, the storage capacity is formed by a light-shielding film and an oxide thereof to minimize its area, and a semiconductor device capable of displaying a bright picture is realized.

Claims

1. A method of manufacturing a semiconductor device having a pixel unit and a drive circuit unit over a same substrate, comprising:

forming a channel-forming region, a source region, a drain region and at least one lightly doped region sandwiched between either of said source and drain region and said channel-forming region in an active layer of NTFT forming said drive circuit unit;

forming a channel-forming region, a source region and a drain region in an active layer of PTFT forming said drive circuit unit; and

forming a channel-forming region, a source region, a drain region, and at least one lightly doped region sandwiched between either of said source and drain region and said channel-forming region in an active layer of pixel TFT forming said pixel unit,

wherein said lightly doped region of said NTFT forming said drive circuit unit is formed to be overlapped on said gate wiring of said NTFT forming said drive circuit unit with said gate insulating film interposed therebetween,

wherein said lightly doped region of said pixel TFT is formed not to be overlapped on said gate wiring of said pixel TFT with said gate insulating film interposed therebetween, and

wherein a storage capacitor in said pixel unit are formed by a light-shielding film formed over said pixel TFT, an oxide of a light-shielding film and a pixel electrode.

3. A method of manufacturing a semiconductor device according to claim 1 or 2, wherein said light-shielding film is an aluminum film or a film comprising mainly aluminum.

4. A method of manufacturing a semiconductor device according to claim 1 or 2, wherein said oxide is an alumina film formed by an anodic oxidation method, a plasma oxidation method or a thermal oxidation method.

5. A method of manufacturing a semiconductor device according to claim 1 or 2, wherein said semiconductor device is an EL display device.

6. A method of manufacturing a semiconductor device according to claim 1 or 2, wherein said semiconductor device is one selected from the group consisting of a portable telephone, a video camera, a personal computer, a goggle-type display, and a projector.

2. A method of manufacturing a semiconductor device having a pixel unit comprising a plurality of pixel TFTs and a drive circuit unit comprising a plurality of drive TFTs over a same substrate, comprising:

forming an active layer comprising a semiconductor film over said substrate;

forming a gate-insulating film on said active layer;

forming an electrically conducting film on said gate-insulating film;

forming a gate wiring of NTFT forming said drive circuit unit by patterning said electrically conducting film;

forming n-type regions in said active layer of NTFT forming said drive circuit unit by adding an element belonging to the Group 15 of periodic table using said gate wiring of said NTFT forming said drive circuit unit as a mask,

forming n-type regions under said gate wiring of said NTFT forming said drive circuit unit by diffusing said n-type regions by heat treatment;

forming a gate wiring of said pixel TFT by patterning said electrically conducting film;

forming n-type regions in said active layer of said pixel TFT by adding an element belonging to the Group 15 of periodic table by using said gate wiring of said pixel TFT as a mask;

forming n+-type regions in said active layers of NTFTs forming said drive circuit unit and in said active layers of said pixel TFT by adding an element belonging to the Group 15 of periodic table;

forming a gate wiring of said PTFT forming said drive circuit unit by patterning said electrically conducting film;

forming p+-type regions in said active layer of PTFT forming said drive circuit unit by adding an element belonging to the Group 13 of periodic table by using said gate wiring of PTFT forming said drive circuit unit as a mask;

forming an interlayer-insulating film comprising a resin film over said NTFT and PTFT forming said drive circuit unit and over said pixel TFT;

forming a light-shielding film on said interlayer-insulating film;

forming an oxide of said light-shielding film on said surface of said light-shielding film; and

forming a pixel electrode in contact with said oxide of said light-shielding film and to be overlapped on said light-shielding film.