Semiconductor device and method for fabricating the same

• US 20030201442A1
• Filed: 04/24/2003
• Published: 10/30/2003
• Est. Priority Date: 04/24/2002
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Makita, Naoki
• Granted Patent: US 7,612,375 B2
• Time in Patent Office: Days
• US Class Current: 257/66
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1229 with different crystal properties within a device or between different devices
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1277 using a crystallisation promoting species, e.g. local introduction of Ni catalyst
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Abstract

A semiconductor device includes at least one thin-film transistor, which includes a semiconductor layer, a gate electrode and a gate insulating film. In the semiconductor layer, a crystalline region, including a channel forming region, a source region and a drain region, is defined. The gate electrode is provided to control the conductivity of the channel forming region. The gate insulating film is provided between the gate electrode and the semiconductor layer. The semiconductor layer includes a gettering region outside of the crystalline region thereof.

Claims

1. A semiconductor device comprising at least one thin-film transistor, the thin-film transistor including:

a semiconductor layer, in which a crystalline region, including a channel forming region, a source region and a drain region, is defined;

a gate electrode for controlling the conductivity of the channel forming region; and

a gate insulating film, which is provided between the gate electrode and the semiconductor layer,

wherein the semiconductor layer includes a gettering region outside of the crystalline region thereof.

2. The device of claim 1, wherein the gettering region is partially amorphous.

3. The device of claim 1, wherein the gettering region is amorphous substantially completely.

4. The device of claim 1, wherein the gettering region includes an amorphous phase at a greater percentage, and a crystalline phase at a smaller percentage, than the channel forming region, the source region or the drain region.

5. The device of claim 1, wherein the semiconductor layer is made of Si, and

wherein the gettering region has a higher Pa/Pc ratio than the channel forming region, where the Pa/Pc ratio is a ratio of a TO phonon peak Pa of amorphous Si to a TO phonon peak Pc of crystalline Si in a Raman spectrum.

6. The device of claim 5, wherein the gettering region has a higher Pa/Pc ratio than the source region or the drain region.

7. The device of claim 1, wherein the gettering region is not adjacent to the channel forming region.

8. The device of claim 1, wherein the gettering region is located outside of a portion of the semiconductor layer, in which an interconnect, connecting respective thin-film transistors together electrically, contacts with the semiconductor layer.

9. The device of claim 1, wherein the gettering region is located at an outer edge of the semiconductor layer, and

wherein the contact portion between the interconnect and the semiconductor layer overlaps with a portion of the gettering region and a portion of the crystalline region.

10. The device of claim 1, wherein the gettering region is located at an outer edge of the semiconductor layer, and

wherein the contact portion between the interconnect and the semiconductor layer overlaps with the crystalline region only.

11. The device of claim 1, wherein multiple thin-film transistors are allocated to the single semiconductor layer and at least two of the thin-film transistors share the source region or the drain region, and

wherein the gettering region is located adjacent to the source region or the drain region that is shared by the at least two thin-film transistors.

12. The device of claim 1, wherein the gettering regions are provided at the outer edges of the semiconductor layer and between the source regions, between the drain regions or between the source and drain regions, and

wherein the contact portion between the interconnect and the semiconductor layer overlaps with a portion of one of the gettering regions and a portion of the crystalline region.

13. The device of claim 1, wherein the gettering regions are provided at the outer edges of the semiconductor layer and between the source regions, between the drain regions or between the source and drain regions, and

wherein the contact portion between the interconnect and the semiconductor layer overlaps with the crystalline region only.

22. The device of claim 1 or 14, wherein the gettering region includes an n-type dopant element belonging to Group Vb of the periodic table and a p-type dopant element belonging to Group IIIb of the periodic table.

23. The device of claim 22, wherein the gettering region includes the n-type dopant element at a concentration of about 1×

10¹⁹/cm³ to about 1×

10²¹/cm³ and the p-type dopant element at a concentration of about 1.5×

10¹⁹/cm³ to about 3×

10²¹/cm³.

24. The device of claim 22, wherein in the gettering region, the concentration of the p-type dopant element is about 1.5 to about 3.0 times as high as that of the n-type dopant element.

25. The device of claim 1 or 14, wherein the gettering region is doped with at least one rare-gas element that is selected from the group consisting of Ar, Kr and Xe.

26. The device of claim 25, wherein the gettering region is doped with the rare-gas element at a dose of about 1×

10¹⁹/cm³ to about 3×

10²¹/cm³.

27. The device of claim 1 or 14, wherein at least one catalytic element that is selected from the group consisting of Ni, Co, Sn, Pb, Pd, Fe and Cu is added to the gettering region.

28. The device of claim 27, wherein the gettering region includes the catalytic element at a dose of at least about 1×

10¹⁹/cm³.

29. The device of claim 1 or 14, wherein the gate electrode is made of at least one material that is selected from the group consisting of W, Ta, Ti and Mo.

59. An electronic appliance comprising the semiconductor device of claim 1.

60. The electronic appliance of claim 59, further comprising a display section that conducts a display operation by using the semiconductor device.

14. A semiconductor device comprising an n-channel thin-film transistor and a p-channel thin-film transistor,

wherein the n-channel thin-film transistor and the p-channel thin-film transistor each include:

a semiconductor layer, in which a crystalline region, including a channel forming region, a source region and a drain region, is defined;

a gate electrode for controlling the conductivity of the channel forming region; and

a gate insulating film, which is provided between the gate electrode and the semiconductor layer, and

wherein the semiconductor layer includes a gettering region outside of the crystalline region thereof.

15. The device of claim 14, wherein the gettering region is partially amorphous.

16. The device of claim 14, wherein the gettering region is amorphous substantially completely.

17. The device of claim 14, wherein the gettering region includes an amorphous phase at a greater percentage, and a crystalline phase at a smaller percentage, than the channel forming region, the source region or the drain region.

18. The device of claim 14, wherein the semiconductor layer is made of Si, and

wherein the gettering region has a higher Pa/Pc ratio than the channel forming region, where the Pa/Pc ratio is a ratio of a TO phonon peak Pa of amorphous Si to a TO phonon peak Pc of crystalline Si in a Raman spectrum.

19. The device of claim 18, wherein the gettering region has a higher Pa/Pc ratio than the source region or the drain region.

20. The device of claim 14, wherein the ratio S/W of the area S of the gettering region in the n-channel thin-film transistor to the width W of the channel forming region thereof is approximately equal to the ratio S/W of the area S of the gettering region in the p-channel thin-film transistor to the width W of the channel forming region thereof.

21. The device of claim 14, wherein a distance L from a junction between the channel forming region and the source region or the drain region to the gettering region in the n-channel thin-film transistor is approximately equal to a distance L from a junction between the channel forming region and the source region or the drain region to the gettering region in the p-channel thin-film transistor.

30. A method for fabricating a semiconductor device, the method comprising the steps of:

preparing an amorphous semiconductor film, to at least part of which a catalytic element, promoting crystallization, has been added;

subjecting the amorphous semiconductor film to a first annealing process, thereby crystallizing at least a portion of the amorphous semiconductor film and obtaining a semiconductor film including a crystalline region;

patterning the semiconductor film into a plurality of island-shaped semiconductor layers, each including the crystalline region;

selectively adding a gettering element to a portion of each said island-shaped semiconductor layer other than portions to be source and drain regions, thereby defining an amorphized gettering region; and

subjecting the island-shaped semiconductor layers to a second annealing process, thereby diffusing at least part of the catalytic element toward the gettering region in each said island-shaped semiconductor layer.

31. The method of claim 30, further comprising the step of keeping the gettering region amorphized.

32. The method of claim 30, further comprising the step of introducing an n-type dopant and/or a p-type dopant into selected portions of each said island-shaped semiconductor layer before the step of subjecting the island-shaped semiconductor layers to the second annealing process is performed.

33. The method of claim 32, wherein the step of introducing the n-type dopant and/or the p-type dopant is performed before the step of adding the gettering element is performed.

34. The method of claim 32, wherein the step of introducing the n-type dopant and/or the p-type dopant is performed after the step of adding the gettering element has been performed.

35. The method of claim 32, comprising the steps of:

forming a gate insulating film over each said island-shaped semiconductor layer;

forming a gate electrode on the gate insulating film; and

introducing the n-type dopant and/or the p-type dopant into portions of the island-shaped semiconductor layer which are not covered with the gate electrode.

36. The method of claim 30, wherein the step of adding the gettering element includes the step of adding at least one element that is selected from the group consisting of Ar, Kr and Xe.

37. The method of claim 30, wherein the step of adding the gettering element includes the step of adding an n-type dopant element belonging to Group Vb of the periodic table and a p-type dopant element belonging to Group IIIb of the periodic table.

38. The method of claim 30, wherein the step of adding the gettering element includes the step of adding the gettering element to the gettering region at a controlled dose of about 1×

10¹⁹/cm³ to about 3×

10²¹/cm³.

45. The method of claim 30, wherein the step of preparing the amorphous semiconductor film includes the step of preparing an amorphous silicon film, and

wherein the step of forming the amorphized gettering region includes the step of setting a Pa/Pc ratio of the gettering region higher than that of the channel forming region, where the Pa/Pc ratio is a ratio of a TO phonon peak Pa of amorphous Si to a TO phonon peak Pc of crystalline Si in a Raman spectrum.

46. The method of claim 30, further comprising the step of forming an interconnect that contacts with a region other than the gettering region after the step of conducting the second annealing process has been performed.

48. The method of claim 30, wherein the step of conducting the second annealing process includes the step of conducting the second annealing process such that the gettering region is not crystallized.

49. The method of claim 30, wherein the step of conducting the second annealing process includes the step of conducting the second annealing process such that the amorphized gettering region includes an amorphous phase at a greater percentage, and a crystalline phase at a smaller percentage, than the channel forming region, source region or drain region.

50. The method of claim 30, wherein the step of conducting the second annealing process includes the step of conducting a rapid thermal annealing (RTA) process.

51. The method of claim 30, wherein the step of preparing the amorphous semiconductor film includes the steps of:

defining a mask having an opening on the amorphous semiconductor film; and

introducing the catalytic element through the opening into a selected area of the amorphous semiconductor film.

52. The method of claim 30, wherein the step of forming the gettering region includes the step of forming the gettering region adjacent to the source region or the drain region of the thin-film transistor, not to the channel forming region thereof.

53. The method of claim 30, wherein the step of forming the gettering region includes the step of forming the gettering region in a region other than where electros or holes travel.

54. The method of claim 30, wherein the step of forming the gettering region includes the step of forming the gettering region at a location that is closer to an outer edge of the island-shaped semiconductor layer than the center of a contact region is, the contact region electrically connecting the island-shaped semiconductor layer to an interconnect.

55. The method of claim 54, wherein the gettering region partially overlaps with the contact region.

56. The method of claim 30, wherein the step of preparing the amorphous semiconductor film includes the step of adding at least one catalytic element, selected from the group consisting of Ni, Co, Sn, Pb, Pd, Fe and Cu, to the amorphous semiconductor film.

57. The method of claim 30, further comprising the step of exposing the semiconductor film to a laser beam after the step of subjecting the amorphous semiconductor film to the first annealing process has been performed.

58. The method of claim 32, wherein the step of conducting the second annealing process activates the dopant that has been introduced into the island-shaped semiconductor layers.

39. A method for fabricating a semiconductor device, the method comprising the steps of:

preparing an amorphous semiconductor film, to at least part of which a catalytic element, promoting crystallization, has been added;

subjecting the amorphous semiconductor film to a first annealing process, thereby crystallizing at least a portion of the amorphous semiconductor film and obtaining a semiconductor film including a crystalline region;

patterning the semiconductor film into a plurality of island-shaped semiconductor layers, each including the crystalline region;

forming a gate insulating film over each said island-shaped semiconductor layer;

forming a gate electrode on the gate insulating film;

introducing a dopant into a selected portion of the island-shaped semiconductor layer, thereby forming an amorphized gettering region in a portion of the island-shaped semiconductor layer other than portions to be source and drain regions; and

subjecting the island-shaped semiconductor layers to a second annealing process, thereby diffusing at least part of the catalytic element toward the gettering region in each said island-shaped semiconductor layer.

40. The method of claim 39, wherein the step of introducing the dopant includes the steps of:

introducing an n-type dopant element into portions of a first one of the island-shaped semiconductor layers to be the source region, drain region and gettering region of an n-channel thin-film transistor and into a portion of a second one of the island-shaped semiconductor layers to be the gettering region of a p-channel thin-film transistor; and

introducing a p-type dopant element into portions of the second island-shaped semiconductor layer to be the source region, drain region and gettering region of the p-channel thin-film transistor and into the portion of the first island-shaped semiconductor layer to be the gettering region of the n-channel thin-film transistor after the step of introducing the n-type dopant element has been performed.

41. The method of claim 39, wherein the step of introducing the dopant includes the steps of:

introducing a p-type dopant element into portions of a first one of the island-shaped semiconductor layers to be the source region, drain region and gettering region of a p-channel thin-film transistor and into a portion of a second one of the island-shaped semiconductor layers to be the gettering region of an n-channel thin-film transistor; and

introducing an n-type dopant element into portions of the second island-shaped semiconductor layer to be the source region, drain region and gettering region of the n-channel thin-film transistor and into the portion of the first island-shaped semiconductor layer to be the gettering region of the p-channel thin-film transistor after the step of introducing the p-type dopant element has been performed.

42. A method for fabricating a semiconductor device, the method comprising the steps of:

preparing an amorphous semiconductor film, to at least part of which a catalytic element, promoting crystallization, has been added;

subjecting the amorphous semiconductor film to a first annealing process, thereby crystallizing at least a portion of the amorphous semiconductor film and obtaining a semiconductor film including a crystalline region;

patterning the semiconductor film into a first island-shaped semiconductor layer and a second island-shaped semiconductor layer, each including the crystalline region;

forming a gate insulating film over each said island-shaped semiconductor layer;

forming a first gate electrode on the gate insulating film on the first island-shaped semiconductor layer, on which an n-channel thin-film transistor will be formed, and a second gate electrode on the gate insulating film on the second island-shaped semiconductor layer, on which a p-channel thin-film transistor will be formed, respectively;

introducing an n-type dopant element into the first and second island-shaped semiconductor layers with the first and second gate electrodes used as a mask, thereby forming a source region, a drain region and a gettering region for the n-channel thin-film transistor and a gettering region for the p-channel thin-film transistor;

forming a first mask, which exposes a portion of the first island-shaped semiconductor layer of the n-channel thin-film transistor, over the first gate electrode, and a second mask, which defines a third gate electrode for the p-channel thin-film transistor, on the second gate electrode, respectively;

patterning the second gate electrode into the third gate electrode by using the second mask;

introducing a p-type dopant element into portions of the first and second island-shaped semiconductor layers, which are not covered with the first mask or the third gate electrode, thereby forming an amorphized gettering region for the n-channel thin-film transistor and the source region, drain region and amorphized gettering region for the p-channel thin-film transistor, respectively; and

conducting a second annealing process such that at least part of the catalytic element in the first and second island-shaped semiconductor layers is introduced into the gettering regions that have been amorphized by being doped with both the p-type dopant element and the n-type dopant element.

44. The method of claim 42 or 43, wherein the step of introducing the n-type dopant element includes the step of introducing the n-type dopant element into the gettering region at a dose of about 1×

10¹⁹/cm³ to about 1×

10²¹/cm³, and

wherein the step of introducing the p-type dopant element includes the step of introducing the p-type dopant element into the gettering region at a dose of about 1.5×

10¹⁹/cm³ to about 3×

10²¹/cm³.

47. The method of claim 42, wherein the step of forming the second gate electrode includes the step of forming the second gate electrode such that the second gate electrode has a width greater than that of the third gate electrode.

43. A method for fabricating a semiconductor device, the method comprising the steps of:

preparing an amorphous semiconductor film, to at least part of which a catalytic element, promoting crystallization, has been added;

subjecting the amorphous semiconductor film to a first annealing process, thereby crystallizing at least a portion of the amorphous semiconductor film and obtaining a semiconductor film including a crystalline region;

patterning the semiconductor film into a first island-shaped semiconductor layer and a second island-shaped semiconductor layer, each including the crystalline region;

forming a gate insulating film over each said island-shaped semiconductor layer;

forming a first gate electrode on the gate insulating film on the first island-shaped semiconductor layer, on which a p-channel thin-film transistor will be formed, and a second gate electrode on the gate insulating film on the second island-shaped semiconductor layer, on which an n-channel thin-film transistor will be formed, respectively;

introducing a p-type dopant element into the first and second island-shaped semiconductor layers with the first and second gate electrodes used as a mask, thereby forming a source region, a drain region and a gettering region for the p-channel thin-film transistor and a gettering region for the n-channel thin-film transistor;

forming a first mask, which exposes a portion of the first island-shaped semiconductor layer of the p-channel thin-film transistor, over the first gate electrode, and a second mask, which defines a third gate electrode for the n-channel thin-film transistor, on the second gate electrode, respectively;

patterning the second gate electrode into the third gate electrode by using the second mask;

introducing an n-type dopant element into portions of the first and second island-shaped semiconductor layers, which are not covered with the first mask or the third gate electrode, thereby forming an amorphized gettering region for the p-channel thin-film transistor and the source region, drain region and amorphized gettering region for the n-channel thin-film transistor, respectively; and

conducting a second annealing process such that at least part of the catalytic element in the first and second island-shaped semiconductor layers is introduced into the gettering regions that have been amorphized by being doped with both the n-type dopant element and the p-type dopant element.