Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

• US 20030201477A1
• Filed: 04/14/2003
• Published: 10/30/2003
• Est. Priority Date: 07/30/1997
• Status: Active Grant

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz
• Granted Patent: US 6,803,299 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

An electrically erasable programmable read only memory (EEPROM) having a non conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the EEPROM device. The non conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. Application of relatively low gate voltages combined with reading in the reverse direction greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region. In addition, the memory cell can be erased by applying suitable erase voltages to the gate and the drain so as to cause electrons to be removed from the charge trapping region of the nitride layer. Similar to programming, a narrower charge trapping region enables much faster erase cycles.

Claims

1. A method of enhancing erasure of a cell having a non-conductive charge trapping layer, the cell having a gate generally over the charge trapping layer, the method comprising:

programming said cell to minimize the width of a trapping region within said charge trapping layer by reading with a minimum voltage on said gate in a direction opposite that of programming.

2. A method of enhancing endurance of a cell having a non-conductive charge trapping layer, the cell having a gate generally over the charge trapping layer, the method comprising:

programming said cell to have a minimum width charge trapping region within said charge trapping layer; and

reading said cell with a minimum voltage on said gate in a direction opposite that of programming.

3. A method of operating a cell having a non-conductive charge trapping layer, the method comprising:

programming said cell to have a narrow charge trapping region within said charge trapping layer;

reading said cell in a direction opposite that of programming; and

erasing said cell such that said cell does not enter deep depletion.

4. A programmable, read only memory device comprising:

two diffusion areas in a substrate and a channel formed therebetween;

a first insulating layer having a given thickness;

a non-conducting charge trapping layer having a thickness of 100 angstroms or less overlaying said first insulating layer; and

a second insulating layer having a thickness that is the same magnitude of order as said first insulating layer, that overlays said charge trapping layer; and

a gate at least above said second insulating layer,

wherein said device is adapted to be read in a direction opposite to that in which it was programmed, and

wherein said device is adapted to be programmed with a voltage on one diffusion area which is substantially lower than a voltage on said gate.

5. A device according to claim 4 and wherein said diffusion areas are symmetric with respect to each other.

6. A device according to claim 4 and wherein charge is storable in a charge storage area of said charge trapping layer, the width of said charge storage area being narrow enough to enable stored charge to be erased from said charge storage area.

7. A method of programming and reading a programmable read only memory (PROM) cell, said PROM cell having a semiconducting substrate, source, drain with a channel therebetween and a gate above said channel at least partially separated therefrom by a nonconducting charge trapping material sandwiched between first and second silicon dioxide layers, said method comprising:

applying programming voltages to said drain and said gate and grounding said source, wherein said programming voltage on said drain is substantially lower than said programming voltage on said gate; and

reading in a reverse direction by applying read voltages to said source and said gate and grounding said drain, and subsequently sensing whether or not current flows through said memory device from said source to said drain.

8. The method according to claim 7, wherein a lower limit for said reading voltage applied to said gate during said step of reading said cell is the voltage at which sufficient inversion is generated in said channel whereby the unprogrammed state can be sensed, an upper limit for said reading voltage applied to said gate during said step of reading said cell is the voltage at which the voltage across a region of said channel beneath the trapped charge in said storage is below the voltage applied to said source during reading of said cell.