Method to fabricate self-aligned source and drain in split gate flash

• US 20030201502A1
• Filed: 04/22/2003
• Published: 10/30/2003
• Est. Priority Date: 02/26/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsieh, Chia-Ta
• Granted Patent: US 8,334,558 B2
• Time in Patent Office: Days
• US Class Current: 257/390
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A new structure is disclosed for source/drain bit lines in arrays of MOSFET devices. Rows of conducting regions are formed by ion implantation through openings adjacent to gate structures and in isolation regions separating columns of active areas of the arrays. The openings are filled with insulating material.

Claims

1. A new structure for source/drain bit lines in arrays of MOSFET devices comprising:

rows of conducting regions formed by ion implantation through openings adjacent to gate structures and in isolation regions separating columns of active areas of said arrays;

said openings filled with insulating material.

2. The structure of claim 1 wherein said MOSFET devices are n-channel devices and said conducting regions are formed to be n-type.

3. The structure of claim 1 wherein said MOSFET devices are p-channel devices and said conducting regions are formed to be p-type.

4. The structure of claim 1 wherein said insulating materials are oxide.

5. The structure of claim 1 wherein said insulating materials are high temperature oxide.

6. A method of fabricating a new structure for source/drain bit lines in arrays of MOSFET devices comprising:

providing a partially processed array of MOSFET devices having active areas arranged in columns which are surrounded by insulator filled isolation regions and having formed, but not patterned, all layers comprising gate structures that are adjacent to source/drain regions, etching, in rows, all layers comprising gate structures that are adjacent to source/drain regions and insulator filled isolation regions to form openings that are aligned in rows passing source/drain positions;

performing ion implantation into the silicon under said openings creating continuous conductive regions forming rows through the silicon substrate under said openings.

filling said openings with insulating material.

7. The method of claim 6 wherein said MOSFET devices are n-channel devices and said conducting regions are formed to be n-type.

8. The structure of claim 6 wherein said MOSFET devices are p-channel devices and said conducting regions are formed to be p-type.

9. The structure of claim 6 wherein said insulating material oxide.

10. The structure of claim 6 wherein said insulating materials are high temperature oxide.

11. A method to fabricate self-aligned source/chain lines in split gate flash memory arrays, comprising:

providing an extensive p-type semiconductor region on a semiconductor substrate;

defining columns of active regions by surrounding said active regions with oxide filled isolation regions;

performing a first threshold voltage adjust implant;

forming a floating gate oxide layer over the surface of said active regions;

forming a poly 1 layer;

forming a photoresist layer and patterning said photoresist layer to etch said poly 1 layer so that after etching said poly 1 is disposed over said active regions;

performing a poly 1 etch;

removing the photoresist layer;

forming sequentially, a first insulating layer, a poly 2 layer, a second insulating layer, a poly 3 layer and a first oxide layer;

forming another photoresist layer and patterning the photoresist to form, upon etching, two kinds of interposed openings in the row direction, i.e., perpendicular to the active region columns;

openings for source/drain lines that could be narrower than openings for erase gates;

etching sequentially, said first oxide layer, said poly 3 layer, said second insulating layer, said poly 2 layer and said first insulating layer;

removing said other photoresist layer;

forming a third photoresist layer and patterning the photoresist so as to deepen, upon etching, only the openings for source/drain lines;

etching poly 1;

etching floating gate oxide and oxide of said isolation regions;

performing a source/drain ion implantation;

removing the third photoresist layer;

forming a second oxide layer and etching said second oxide layer so that the source/drain openings are filled with said second oxide and so that sidewall spacers, composed of said second oxide, remain,

etching exposed poly 1 and poly 3;

performing a second threshold adjust implant for the erase gates;

etching exposed floating gate oxide;

forming an erasing gate oxide layer;

forming a poly 4 layer;

forming a fourth photoresist layer and patterning the photoresist for erase gate lines, in the column direction, disposed over the active regions;

etching poly 4;

removing the fourth photoresist layer.

12. The method of claim 11 wherein said p-type semiconductor region is a p-substrate.

13. The method of claim 11 wherein said p-type semiconductor region is a p-well.

14. The method of claim 11 wherein said isolation regions are shallow trench isolation regions.

15. The method of claim 11 wherein said first threshold voltage adjust implant is performed using Boron ions at energy of about 20 keV and a dose of about 5E11 per sq.cm.

16. The method of claim 11 wherein said floating gate oxide is formed to a thickness of about 150 Angstroms.

17. The method of claim 11 wherein said poly 1 layer is formed to a thickness of about 800 Angstroms.

18. The method of claim 11 wherein said first insulating layer is an ONO layer in which the bottom oxide layer is about 75 Angstroms thick, the silicon nitride layer is about 150 Angstroms thick and the top oxide layer is about 30 Angstroms thick.

19. The method of claim 11 wherein said poly 2 layer is formed to a thickness of about 1000 Angstroms.

20. The method of claim 11 wherein said second insulating layer is a silicon nitride layer that is about 1500 Angstroms thick.

21. The method of claim 11 wherein said poly 3 layer is formed to a thickness of about 500 Angstroms.

22. The method of claim 11 wherein said first oxide layer is a TEOS layer formed to a thickness of about 250 Angstroms.

23. The method of claim 11 wherein said source/drain openings are about 500 to about 2000 Angstroms wide.

24. The method of claim 11 wherein said erase gate openings are about 500 to about 2000 Angstroms wide.

25. The method of claim 11 wherein said source/drain ion implantation is performed using Arsenic ions at energy of about 50 keV and a dose of about 3E15 per sq.cm.

26. The method of claim 11 wherein said second oxide layer is an HTO layer formed to a thickness of about 500 Angstroms.

27. The method of claim 11 wherein said second threshold voltage adjust implant is performed using BF2 ions at energy of about 60 keV and a dose of about 1E13 per sq.cm.

28. The method of claim 11 wherein said erase gate oxide is formed to a thickness of about 250 Angstroms.

29. The method of claim 11 wherein said poly 4 layer is formed to a thickness of about 1500 Angstroms.