Semiconductor device having improved alignment of an electrode terminal on a semiconductor chip and a conductor coupled to the electrode terminal

• US 20030201522A1
• Filed: 04/10/2003
• Published: 10/30/2003
• Est. Priority Date: 02/04/2000
• Status: Active Grant

• Current Assignee: Mitsuo Usami
• Original Assignee: Mitsuo Usami
• Inventors: Usami, Mitsuo
• Granted Patent: US 6,867,478 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: G06K 19/07745 Mounting details of integrated circuit chips
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/0775 arrangements for connecting the integrated circuit to the antenna
• CPC Class Codes: G06K 19/07779 the inductive antenna being a coil
• CPC Class Codes: G06K 19/07786 the antenna being of the HF type, such as a dipole
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68354 used to support diced chips prior to mounting
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/49855 for flat-cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/07811 Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: Y10S 257/91 Diode arrays, e.g. diode read-only memory array
• CPC Class Codes: Y10S 438/928 Front and rear surface processing

Abstract

A semiconductor device manufacturing method is used for packaging a thin semiconductor chip in an economical manner. A semiconductor chip having one electrode terminal, a first member having a first conductor on its surface, and a second member having a second conductor on its surface are prepared. The first and second members are positioned such that the first and second conductors face each other, and the semiconductor chip is held between the members. In this arrangement, one of the first and second conductors is in electrical contact with the first electrode.

Claims

1. A semiconductor device manufacturing method comprising the steps of:

preparing a semiconductor chip having one electrode terminal, a first member having a first conductor on its surface, and a second member having a second conductor on its surface; and

positioning said first and second members such that said first and second conductors face to each other, and holding said semiconductor chip between said members, thereby bringing said first or second conductor into electrical contact with said one electrode terminal.

2. The semiconductor device manufacturing method according to claim 1, further comprising the steps of:

preparing chip alignment means having plural chip alignment holes or grooves each having a size greater than a plane shape of said semiconductor chip; and

performing alignment of said semiconductor chip by setting said semiconductor chip in said hole or groove, and holding said semiconductor chip between said first and second members.

3. The semiconductor device manufacturing method according to claim 1, wherein said first and second conductors are antennas.

4. A The semiconductor device manufacturing method according to claim 1, wherein said alignment hole or groove permits said semiconductor chip to be turned over or rotated 90°

or 180° and

set in said hold or groove.

5. The semiconductor device manufacturing method according to claim 1, wherein said first member includes first and second radiation antennas, respectively electrically-connectable with first and second electrodes of said semiconductor chip.

6. The semiconductor device manufacturing method according to claim 1, wherein an insulating layer is formed on a surface of said semiconductor chip where no electrode is formed.

7. A semiconductor device wherein, upon establishment of electrical connection, between one electrode terminal of a semiconductor chip having an approximately rectangular or square plane shape and a first conductor member, by aligning said first conductor member with said first conductor member, said one electrode includes a pair of electrode terminals such that electrical connection can be made in a case where said semiconductor chip is rotated 90°

and in a case where said semiconductor chip is not rotated, and wherein said semiconductor chip and said first conductor member are electrically connected with each other.

8. The semiconductor device according to claim 7, wherein said pair of electrode terminals are provided on a plane of said semiconductor chip symmetrically with respect to a central point or central axis, or provided symmetrically near four corners.

9. The semiconductor device according to claim 7, wherein said pair of electrode terminals are formed on said plane in a thin line shape.

10. The semiconductor device according to claim 9, wherein a portion of said first conductor member near a connection portion with said electrode terminal has a width less than an interval between said pair of electrode terminals formed in a thin line shape.

11. The semiconductor device according to claim 7, wherein a portion of said first conductor member near a connection portion with said electrode terminal has a shape connectable with on said one of said pair of electrode terminals but unconnectable with the other one of said pair of electrode terminals.

12. The semiconductor device according to claim 7, wherein said pair of electrode terminals are provided on a plane of said semiconductor chip symmetrically with respect to a central point or a central axis, and wherein a portion of said first conductor member near a connection portion with said electrode terminal has a width equal to or less than the half of a width of the plane of said semiconductor chip.

13. The semiconductor device according to claim 7, wherein said pair of electrode terminals are provided near corners of a plane of said semiconductor chip symmetrically with respect to a central point or a central axis on said plane.

14. The semiconductor device according to claim 7, wherein another conductor member apart from said first conductor member is electrically connected to another electrode terminal.

15. A semiconductor device manufacturing method comprising the steps of:

upon establishment of electrical connection between one electrode terminal of a semiconductor chip having an approximately rectangular or square plane shape and a first conductor member, by aligning said first conductor member with said first conductor member, aligning said semiconductor chip by setting said semiconductor chip in a member having a groove or hole which can accommodate said semiconductor chip; and

aligning said semiconductor chip with said first conductor member including a pair of electrode terminals such that electrical connection can be made in a case where said semiconductor chip is rotated 90° and

in a case where said semiconductor chip is not rotated, thereby electrically connecting said semiconductor chip with said first conductor member.