Semiconductor devices including protective layers on active surfaces thereof

• US 20030201531A1
• Filed: 05/08/2003
• Published: 10/30/2003
• Est. Priority Date: 06/08/2000
• Status: Active Grant

• Current Assignee: Alan G. Wood, Warren M. Farnworth
• Original Assignee: Alan G. Wood, Warren M. Farnworth
• Inventors: Farnworth, Warren M., Wood, Alan G.
• Granted Patent: US 7,067,901 B2
• Time in Patent Office: Days
• US Class Current: 257/725
• CPC Class Codes: B33Y 10/00 Processes of additive manufacturing
• CPC Class Codes: B33Y 30/00 Apparatus for additive manufacturing; Details thereof or accessories therefor
• CPC Class Codes: B33Y 80/00 Products made by additive manufacturing
• CPC Class Codes: H01L 21/44 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 23/3157 Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A stereolithographic method of applying material to form a protective layer on a preformed semiconductor die with a high degree of precision, either in the wafer stage, when attached to a lead frame, or to a singulated, bare die. The method is computerized and may utilize a machine vision feature to provide precise die-specific alignment. A semiconductor die may be provided with a protective structure in the form of at least one layer or segment of dielectric material having a controlled thickness or depth and a very precise boundary. The layer or segment may include precisely sized, shaped and located apertures through which conductive terminals, such as bond pads, on the surface of the die may be accessed. A plurality of discrete protective structures may be formed on corresponding semiconductor devices that are carried by a large-scale semiconductor substrate. Dielectric material may also be employed as a structure to mechanically reinforce the die-to-lead frame attachment.

Claims

1. A semiconductor wafer including a plurality of semiconductor device components, each semiconductor device component of said plurality having a protective layer on selected portions thereof, said protective layer on one of said plurality of semiconductor device components being substantially discontinuous from protective layers on adjacent ones of said plurality of semiconductor device components.

2. The semiconductor wafer of claim 1, wherein each of said plurality of semiconductor device components comprises conductors, said conductors of at least selected ones of said plurality of semiconductor device components being exposed through said protective layer.

3. The semiconductor wafer of claim 2, wherein said conductors comprise bond pads.

4. The semiconductor wafer of claim 1, wherein said at least a portion of protective layer comprises a thermoplastic material.

5. The semiconductor wafer of claim 4, wherein said thermoplastic material comprises an adhesive.

6. The semiconductor wafer of claim 1, wherein at least one said protective layer substantially covers an active surface of a corresponding semiconductor device component of said plurality of semiconductor device components.

7. The semiconductor wafer of claim 6, wherein each said protective layer substantially covers an active surface of a corresponding semiconductor device component of said plurality of semiconductor device components.

8. The semiconductor wafer of claim 1, wherein at least one said protective layer comprises a plurality of superimposed, contiguous, mutually adhered layers.

9. The semiconductor wafer of claim 8, wherein each said protective layer comprises a plurality of superimposed, contiguous, mutually adhered layers.

10. The semiconductor wafer of claim 8, wherein all layers of said plurality of superimposed, contiguous, mutually adhered layers that underlie an outermost layer of said plurality of superimposed, contiguous, mutually adhered layers comprise the same material.

11. A semiconductor device component, comprising:

a substrate with at least one conductor on an active surface thereof; and

a plurality of layers of at least semisolid photopolymer material on the active surface, said plurality of layers being of superimposed, contiguous, and mutually adhered, each layer of said plurality of layers being substantially free of voids and air pockets, said at least one conductor being electrically exposed through said plurality of layers.

12. The semiconductor device component of claim 11, wherein said at least one conductor is laterally surrounded by said at least semisolid photopolymer material of at least some layers of said plurality of layers.

13. The semiconductor device component of claim 12, wherein said at least one conductor is recessed beneath an outermost of said plurality of layers.

14. The semiconductor device component of claim 11, wherein a surface of an outermost layer of said plurality of layers is planar.

15. The semiconductor device component of claim 11, wherein a surface of an outermost layer of said plurality of layers is substantially parallel to said active surface.

16. The semiconductor device component of claim 11, wherein said substrate comprises a semiconductor die.

17. The semiconductor device component of claim 11, wherein said substrate comprises a wafer with a plurality of semiconductor device components.

18. The semiconductor device component of claim 17, wherein each of said plurality of layers exhibits a discontinuous region located over streets of said wafer between adjacent semiconductor device components.

19. The semiconductor device component of claim 18, wherein each of said plurality of layers substantially covers an active surface of a corresponding substrate.

20. The semiconductor device component of claim 11, wherein at least an outermost of said plurality of layers comprises an adhesive material.

21. The semiconductor device component of claim 20, wherein said adhesive material comprises thermoplastic material.

22. The semiconductor device component of claim 11, wherein all layers of said plurality of layers comprise the same type of material that underlie an outermost layer of said plurality of layers comprise the same material.