Power amplifier protection circuit

• US 20030201835A1
• Filed: 04/26/2002
• Published: 10/30/2003
• Est. Priority Date: 04/26/2002
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Dening, David, Muhonen, Kathleen
• Granted Patent: US 6,720,831 B2
• Time in Patent Office: Days
• US Class Current: 330/298
• CPC Class Codes: H03F 1/52 Circuit arrangements for protecting such amplifiers monitoring arrangements G01R31/28; increasing reliability in communication systems, e.g. using redundancy H04B1/74
• CPC Class Codes: H03F 3/19 with semiconductor devices only

Abstract

A power amplifier circuit comprises a sensing circuit and a processing circuit adapted to detect voltage peaks in an output of a power amplifier. If the voltage peak is above a predetermined threshold level, the processing circuit acts to reduce bias provided to the power amplifier, thereby reducing the output levels.

Claims

1. A power amplifier circuit comprising:

a power amplifier;

a sensing circuit adapted to detect voltage peaks emitted by said power amplifier; and

a processing circuit receiving an input from said sense circuit and damping said power amplifier to reduce said voltage peaks.

2. The power amplifier circuit of claim 1 wherein said sensing circuit comprises a transistor,

3. The power amplifier circuit of claim 1 wherein said sensing circuit comprises a plurality of diodes.

4. The power amplifier circuit of claim 1 wherein said processing circuit comprises a current mirror.

5. The power amplifier circuit of claim 4 wherein said current mirror acts to reduce bias current supplied to said power amplifier, thereby damping said power amplifier to reduce said voltage peaks.

6. The power amplifier circuit of claim 1 wherein said processing circuit turns off a bias source adapted to bias the power amplifier.

7. The power amplifier circuit of claim 1 wherein said processing circuit shunts a portion of a bias current from the power amplifier to ground, thereby reducing the bias applied to the power amplifier.

8. A method of controlling a power amplifier comprising:

sensing an output of said power amplifier with a sensing circuit; and

reducing bias supplied to said power amplifier to reduce said output when said output exceeds a predetermined threshold.

9. The method of claim 8 wherein sensing an output of said power amplifier comprises sensing the output with an avalanche diode.

10. The method of claim 8 wherein sensing an output of said power amplifier comprises sensing the output with a diode.

11. The method of claim 8 wherein sensing an output of said power amplifier comprises sensing the output with a transistor.

12. The method of claim 8 wherein reducing bias supplied to said power amplifier comprises turning off a bias circuit.

13. The method of claim 8 wherein reducing bias supplied to said power amplifier comprises shunting a portion of a bias current to ground.

14. The method of claim 8 wherein reducing bias supplied to said power amplifier comprises mirroring a current from said sensing circuit across a current mirror.

15. A power amplifier circuit comprising:

a power amplifier comprising an input and an output;

a sensing circuit coupled to said output and detecting peaks in said output, said sensing circuit generating a control signal when a peak is detected; and

a processing circuit receiving said control signal and adjusting a bias signal supplied to said power amplifier to reduce peaks in said output.

16. A power amplifier circuit comprising:

a power amplifier comprising an input and an output;

a transistor coupled to said output and sensing voltage peaks in said output; and

a current mirror coupled to said transistor and said input, said current mirror adjusting bias supplied to said input based on voltage peaks detected by said transistor.