Digital to analog converter

• US 20030201923A1
• Filed: 04/09/2003
• Published: 10/30/2003
• Est. Priority Date: 10/18/2000
• Status: Active Grant

• Current Assignee: Linear Cell Design Co., Ltd.
• Original Assignee: Linear Cell Design Co., Ltd.
• Inventors: Uno, Masayuki
• Granted Patent: US 6,906,653 B2
• Time in Patent Office: Days
• US Class Current: 341/150
• CPC Class Codes: G06G 7/14 for addition or subtraction of vector quantities G06G7/22 ; computing the average by addition; differential amplifiers H03F3/45
• CPC Class Codes: H03M 1/0682 using a differential network structure, i.e. symmetrical with respect to ground
• CPC Class Codes: H03M 1/68 with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

D/A converter of this invention including n+1 capacitors in total consisting of one terminating capacitor (C0) and n binary-weighted capacitors (C1-4) that are subjected to binary weighting ratio of 1:2:4: . . . :2⁽ⁿ⁻¹⁾, and, an inverting amplifier (INV1), further comprising: a feedback switching means (SWR5) provided between the input and output of the inverting amplifier (INV1); a switching means for terminating operation (SWR0) supplies one of two main reference voltages (VB,VT) to the terminating capacitor (C0), and then, makes connection of the terminating capacitor (C0) to the output of the inverting amplifier (INV1); a plurality of switching means for input operation (SWD1-4,SWR1-4) makes selection of one of the two main reference voltages (VB,VT) to be provided for the n binary-weighted capacitors (C1-4) depending on digital data (D1-4), and then, makes connection of the second terminal side of the n binary-weighted capacitors (C1-4) to the output of the inverting amplifier (INV1).

Claims

1. D/A converter including n+1 (n is a natural number) capacitors in total consisting of one terminating capacitor (C0) serving as a unit capacitor and n binary-weighted capacitors (C1-4) that are subjected to binary weighting to the unit capacitor in the ratio of 1:

2;

4;

. . . ;

2<sup>(n−

1)</sup>, and, an inverting amplifier (INV1) for obtaining amplified output, the input terminal of the inverting amplifier being connected to first terminal side of the n+1 capacitors in common,

further comprising;

a feedback switching means (SWR5) provided between the input and output of the inverting amplifier (INV1)and being in a closed state on reset operation period (T1) and in an open state on output operation period (T2);

a switching means for terminating operation (SWR0) supplies one of two main reference voltages (VB, VT) to second terminal side of the terminating capacitor (C0) on the reset operation period (T1), and then, makes connection of the second terminal side of the terminating capacitor (C0) to the output of the inverting amplifier (INV1) on the output operation period (T2);

a plurality of switching means for input operation (SWD1-4,SWR1-4) makes selection of one of the two main reference voltages (VB,VT) to be provided for the second terminal side of the n binary-weighted capacitors (C1-4) depending on digital data (D1-4) on the reset operation period (T1), and then, makes connection of the second terminal side of the n binary-weighted capacitors (C1-4) to the output of the inverting amplifier (INV1)on the output operation period (T2).

6. D/A converter including two D/A converter portions (DAC1A,DAC1B) having same structure with that of D/A converter set forth in claim1 in parallel, further comprising:

one holding means (SH1A,SWrefa) for holding the output of one of the inverting amplifier (INV1A) on the output operation period (T2) and then supplying it as one of the main reference voltages (VB,VT) on next reset operation period (T3);

the other holding means (SH1B,SWrefb) for holding the output of the other of the inverting amplifier (INV1B) on the output operation period (T2) and then supplying it as the other of the main reference voltages (VB,VT) on next reset operation period (T3);

wherein said one of the main reference voltages (VB,VT) is provided for the second terminal side of the terminating capacitors (C0a) by switching means for terminating operation (SWR0a) on the reset operation period (T1) and the other of the main reference voltages (VB,VT) is provided for the second terminal side of the terminating capacitors (C0b) by the switching means for terminating operation (SwR0b) on the reset operation period (T1), and

the plurality of switching means for input operation (SWD1a-4a, SWR1a-4a, SWD1b-4b, SWR1b-4b) makes selection of said one or the other of the two main reference voltages (VB,VT) to be provided for the second terminal side of the n binary-weighted capacitors (C1a-4a, C1b-4b) depending on upper bits of digital data (D1-4) on the reset operation period (T1), and then, makes connection of the second terminal side of the n binary-weighted capacitors (C1a-4a, C1b-4b) to the output of the inverting amplifier (INV1A,INV1B) on the output operation period (T2),

after that, the output of the inverting amplifier (INV1A) on the output operation period (T2) is provided for the second terminal side of the terminating capacitor (C0a) by said one holding means (SH1A,SWrefa) and the output of the inverting amplifier (INV1B) on the output operation period (T2) is provided for the second terminal side of the terminating capacitor (C0b) by the other holding means (SH1B,SWrefb) on the next reset operation period (T3), and then, switching means for terminating operation (SWR0a,SWR0b) makes connection of the second terminal side of the terminating capacitors (C0a,C0b) to the outputs of the inverting amplifiers (INV1A, INV1B) on next output operation period (T4),

the plurality of switching means for input operation (SWD1a-4a, SWD1b-4b, SWR1b-4b, SWR1b-4b) makes selection of said one or the other of the output of the inverting amplifiers (INV1A,INV1B) on the output operation period (T2) to be provided for the second terminal side of the n binary-weighted capacitors (C1a-4a,C1b-4b) depending on lower bits of digital data (D5-8, or,D9-12) on the next reset operation period (T3), and then, makes connection of the second terminal side of the n binary-weighted capacitors (C1-4) to the outputs of the inverting amplifiers (INV1A, INV1B) on the next output operation period (T4).

7. D/A converter set forth in claim 1-6,

wherein the inverting. amplifier is fully differential operational amplifier with 2 sets of the input and the output,

the inverting amplifier having 2 sets of D/A converter portions (DACa,DACb) corresponding to the 2 sets of the input and output of the inverting amplifier,

the D/A converter portions comprising the n+1 capacitors, the feedback switching means, the switching means for terminating operation, and the plurality of switching means for input operation respectively,

the two main reference voltages (VB,VT) are provided for the 2 sets of D/A converter portions (DACa,DACb) in opposite way of connections for each other.

2. D/A converter including n+1 (n is a natural number) capacitors in total consisting of one terminating capacitor (C0) serving as a unit capacitor and n binary-weighted capacitors (C1-4) that are subjected to binary weighting to the unit capacitor in the ratio of 1:

2;

4;

. . . ;

2<sup>(n−

1)</sup>, and, an inverting amplifier (INV1) for obtaining amplified output, the input terminal of the inverting amplifier being connected to first terminal side of the n+1 capacitors in common;

further comprising;

a feedback switching means (SWR5) provided between the input and output of the inverting amplifier (INV1)and being in a closed state on reset operation period (T1) and in an open state on output operation period (T2);

a switching means for terminating operation (SWR0) supplies one of sub reference voltages (VM) obtainable by voltage dividing of two main reference voltages (VB,VT) to second terminal side of the terminating capacitor (C0) on the reset operation period, and then, makes connection of the second terminal side of the terminating capacitor (C0) to the output of the inverting amplifier (INV1)on the output operation period;

a plurality of switching means for input operation (SWD1-4,SWR1-4) makes selection of one of the two main reference voltages (VB,VT) to be provided for the second terminal side of the n binary-weighted capacitors (C1-4) depending on upper bits of digital data (D1-4) on the reset operation period, and then, makes connection of the second terminal side of the n binary-weighted capacitors (C1-4) to the output of the inverting amplifier (INV1) on the output operation period; and

,

sub reference voltage supply means (SUB) for selecting one of m−

1 (m is a natural number of 2 or greater) sub reference voltage values obtained by dividing equally into m aliquots between the two main reference voltages (VB,VT) as the sub reference voltage (VM) depending on lower bits of the digital data (D5-8).

3. D/A converter set forth in claim 2, said sub reference voltage supply means (SUB) being another D/A converter (DAC2), comprising;

n′

+1 (n′

is a natural number) capacitors in total consisting of one terminating capacitor (C5) serving as a unit capacitor and n′

binary-weighted capacitors (C6-9) that are subjected to binary weighting to the unit capacitor in the ratio of 1;

2;

4;

. . . ;

2<sup>(n′

−

1)</sup>;

an inverting amplifier (INV2) for obtaining amplified output, a input terminal of which is connected to first terminal side of the n′

+1 capacitors in common;

a feedback switching means (SWR11) provided between the input and output of the inverting amplifier (INV2) and being in a closed state on previous output period (T2) and in an open state on the reset operation period (T1);

a switching means for terminating operation (SWR6) supplies one of two main reference voltages (VB,VT) to second terminal side of the terminating capacitor (C5) on the previous output operation period (T2), and then, makes connection of the second terminal side of the terminating capacitor (C5) to the output of the inverting amplifier (INV2) on the reset operation period (T1); and

,

a plurality of switching means for input operation (SWD5-8, SWR7-10) makes selection of one of the two main reference voltages (VB,VT) to be provided for the second terminal side of the n′

binary-weighted capacitors (C6-9) depending on lower bits of the digital data (D5-8) on the previous output operation period (T2), and then, makes connection of the second terminal side of the n′

binary-weighted capacitors (C6-9) to the output of the inverting amplifier (INV2) on the reset operation period (T1);

whereby the inverting amplifier (INV2) outputs the sub reference voltage (VM).

4. D/A converter set forth in claim 2, said sub reference voltage supply means (SUB) comprising;

a switching means (SWT) for providing the terminating capacitor (C0) with one of the main reference voltages (VB,VT) instead of the sub reference voltage (VM) on first reset operation period (T5), and

a sample-hold circuit (SH1) holding the output (VM(t1a), VM(t1b)) of the inverting amplifier on the previous output operation period (T6,T4) and then, providing the output (VM(t1a), VM(t1b)) of the inverting amplifier as the sub reference voltage (VM) on the reset operation period (T3, T1).

5. D/A converter set forth in claim 2, said sub reference voltage supply means (SUB) comprising;

means (SWT′

) for providing to the second terminal side of the terminating capacitor (C0) with one of the main reference voltages (VB,VT) instead of the sub reference voltage (VM) on first reset operation period (T3), and holding the electric charge of the terminating capacitor (C0) on the reset operation period (T1), the electric charge being obtained by connection of the second terminal side of the terminating capacitor to the output (VM(t1)) of the inverting amplifier on previous output operation period (T4).