Generating pulse width modulated waveforms to digitally drive pixels

• US 20030201986A1
• Filed: 04/30/2002
• Published: 10/30/2003
• Est. Priority Date: 04/30/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Willis, Thomas E., OʼConnor, Michael
• Granted Patent: US 7,113,195 B2
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0828 forming a digital to analog [D/A] conversion circuit
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 2310/0259 with use of an analog or digital ramp generator in the column driver or in the pixel circuit
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

An array of display elements (e.g., pixels) in a display device (e.g., a spatial light modulator) may be digitally driven using pulse width modulated waveforms. Pulse width modulated waveforms may be locally generated to controllably drive each pixel in display systems with digital storage. A pixel drive circuit having a waveform generator may receive first digital data indicative of an optical output from an associated first display element. Moreover, second digital data indicative of a common reference with respect to a second display element may also be received at the first display element for comparison purposes. As a result, in one embodiment, a pulse width modulated waveform that includes only a single transition separating a first pulse interval and a second pulse interval may be generated based on a pixel value and a global count value instead of relying upon adding up multiple non-overlapping waveforms to drive a pixel.

Claims

1. A method, comprising:

receiving at a first display element first digital data indicative of an optical output from the first display element;

receiving at the first display element second digital data indicative of a common reference with respect to a second display element; and

generating for said first display element a modulated signal including one transition separating a first pulse interval from a second pulse interval based on said first and second digital data.

2. The method of claim 1, including:

comparing said first digital data to said second digital data to provide an indication of a comparison between said first and second digital data; and

driving the first display element from the modulated signal to provide the optical output based on said comparison.

3. The method of claim 2, including deriving said one transition to form the modulated signal within a refresh period based on said indication.

4. The method of claim 3, including illuminating the first display element for a duration within said refresh period based on said one transition.

5. The method of claim 2, further including asserting a first signal to:

start a frame within said refresh period; and

set the modulated signal to an “

ON”

logic state at the beginning of said frame.

6. The method of claim 5, including asserting a second signal to:

selectively load said first digital data at the first display element; and

dynamically update said second digital data.

7. The method of claim 6, including providing a third signal based on said indication from the comparison causing said one transition from said “

ON”

logic state to said “

OFF”

logic state when said first and second digital data are substantially equal.

8. The method of claim 6, including providing a fourth signal based on said indication from the comparison causing said one transition from said “

OFF”

logic state to said “

ON”

logic state when said first and second digital data are different.

9. The method of claim 1, further including:

receiving said first digital data including a current pixel value in at least one register associated with the first display element in parallel;

receiving said second digital data including a current count value at the first display element in parallel; and

performing pulse width modulation based on a parallel comparison of said current pixel value and said current count value to indicate said one transition.

10. The method of claim 1, further including:

serially receiving said first digital data including a current pixel value in at least one register associated with the first display element;

serially receiving said second digital data including a current count value at the first display element; and

performing pulse width modulation based on a serial comparison of said current pixel value and said current count value to indicate said one transition.

11. An apparatus, comprising:

a first display element; and

a waveform generator operably coupled to the first display element to receive at the first display element first digital data indicative of an optical output from the first display element and second digital data indicative of a common reference with respect to a second display element to generate for said first display element a modulated signal including one transition separating a first pulse interval from a second pulse interval based on said first and second digital data.

12. The apparatus of claim 11, wherein said waveform generator to:

compare said first digital data to said second digital data to provide an indication of a comparison between said first and second digital data; and

drive the first display element from the modulated signal to provide the optical output based on said comparison.

13. The apparatus of claim 12, further comprising:

a storage device operably coupled to the waveform generator to receive said first digital data, wherein said waveform generator to;

derive said one transition to form the modulated signal within a refresh period based on said indication; and

illuminate the first display element for a duration within said refresh period based on said one transition.

14. The apparatus of claim 13, wherein said waveform generator to receive:

a first signal to start a frame within said refresh period and set the modulated signal to an “

ON”

logic state at the beginning of said frame; and

a second signal to selectively load said first digital data at the first display element and dynamically update said second digital data.

15. The apparatus of claim 13, wherein the first display element includes a plurality of display elements forming an array of display elements in a liquid crystal display.

16. The apparatus of claim 15, wherein said liquid crystal display includes a spatial light modulator.

17. The apparatus of claim 13, wherein said waveform generator to receive:

a third signal based on said indication from the comparison causing said one transition from said “

ON”

logic state to said “

OFF”

logic state when said first and second digital data are substantially equal; and

a fourth signal based on said indication from the comparison causing said one transition from said “

OFF”

logic state to said “

ON”

logic state when said first and second digital data are different.

18. The apparatus of claim 17, wherein said waveform generator includes a comparator to compare said first digital data with said second digital data to provide said one transition in the modulated signal driving the first display element.

19. The apparatus of claim 18, wherein said waveform generator includes:

a first bus to receive said first digital data including a current pixel value in at least one register associated with the first display element in parallel;

a second bus to receive said second digital data including a current count value at the first display element in parallel; and

pulse width modulation circuitry to form said modulated signal based on said one transition in parallel, said pulse width modulation circuitry to perform pulse width modulation based on a parallel comparison of said current pixel value and said current count value to indicate said one transition.

20. The apparatus of claim 18, wherein said waveform generator includes:

a first port to serially receive said first digital data including a current pixel value in at least one register associated with the first display element;

a second port to serially receive said second digital data including a current count value at the first display element; and

pulse width modulation circuitry to serially form said modulated signal based on said one transition, said pulse width modulation circuitry to perform pulse width modulation based on a serial comparison of said current pixel value and said current count value to indicate said one transition.

21. A processor-based system, comprising:

a plurality of pixel cells forming a pixel array; and

a plurality of drive circuits each drive circuit associated with a different pixel cell of the pixel array to receive first digital data indicative of an optical output from said different pixel cell and receive second digital data indicative of a common reference for said plurality of pixel cells to generate for said different pixel cell a modulated signal including one transition separating a first pulse interval from a second pulse interval based on said first and second digital data.

22. The processor-based system of claim 21, wherein said each drive circuit comprising:

a waveform forming device to generate the modulated signal through pulse width modulation that drives said different pixel cell of the pixel array causing the optical output based on said first and second digital data associated with said different pixel cell of the pixel array.

23. The processor-based system of claim 22, wherein said each drive circuit further comprising a digital storage device operably coupled to the waveform forming device to receive said first and second digital data associated with said different pixel cell of the pixel array, wherein said each drive circuit to:

compare said first digital data to said second digital data to provide an indication of a comparison between said first and second digital data;

drive the first display element from the modulated signal to provide the optical output based on said comparison;

derive said one transition to form the modulated signal within a refresh period based on said indication; and

illuminate the first display element for a duration within said refresh period based on said one transition.

24. The processor-based system of claim 23, wherein said each digital storage device to dynamically receive corresponding said first and second digital data associated with said different pixel cell to cause a duration of illumination for said different pixel cell of the pixel array based on the length of the first pulse interval of the modulated signal within said refresh period.

25. The processor-based system of claim 23, wherein said pixel array includes a liquid crystal display.

26. The processor-based system of claim 25, wherein said liquid crystal display includes a spatial light modulator.

27. The processor-based system of claim 23, wherein said each drive circuit to receive:

a first signal to start a frame within said refresh period and set the modulated signal to an “

ON”

logic state at the beginning of said frame; and

a second signal to selectively load said first digital data at the first display element and dynamically update said second digital data.

28. The processor-based system of claim 27, wherein said each drive circuit includes a comparator to compare corresponding said first digital data with said second digital data to provide said one transition in the modulated signal for said different pixel cell of said pixel array.

29. The processor-based system of claim 28, wherein said each drive circuit to receive:

a third signal based on said indication from the comparison causing said one transition from said “

ON”

logic state to said “

OFF”

logic state when said first and second digital data are substantially equal; and

a fourth signal based on said indication from the comparison causing said one transition from said “

OFF”

logic state to said “

ON”

logic state when said first and second digital data are different.

30. The processor-based system of claim 23, wherein said each digital storage device includes at least one register to store corresponding said first and second digital data associated with said different pixel cell.